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iommu/ipmmu-vmsa: Allow two bit SL0
Introduce support for two bit SL0 bitfield in IMTTBCR by using a separate feature flag. Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
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@ -45,6 +45,7 @@ struct ipmmu_features {
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bool has_cache_leaf_nodes;
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unsigned int number_of_contexts;
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bool setup_imbuscr;
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bool twobit_imttbcr_sl0;
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};
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struct ipmmu_vmsa_device {
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@ -144,6 +145,10 @@ static struct ipmmu_vmsa_device *to_ipmmu(struct device *dev)
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#define IMTTBCR_TSZ0_MASK (7 << 0)
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#define IMTTBCR_TSZ0_SHIFT O
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#define IMTTBCR_SL0_TWOBIT_LVL_3 (0 << 6)
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#define IMTTBCR_SL0_TWOBIT_LVL_2 (1 << 6)
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#define IMTTBCR_SL0_TWOBIT_LVL_1 (2 << 6)
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#define IMBUSCR 0x000c
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#define IMBUSCR_DVM (1 << 2)
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#define IMBUSCR_BUSSEL_SYS (0 << 0)
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@ -396,6 +401,7 @@ static void ipmmu_domain_free_context(struct ipmmu_vmsa_device *mmu,
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static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
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{
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u64 ttbr;
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u32 tmp;
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int ret;
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/*
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@ -449,9 +455,14 @@ static int ipmmu_domain_init_context(struct ipmmu_vmsa_domain *domain)
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* We use long descriptors with inner-shareable WBWA tables and allocate
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* the whole 32-bit VA space to TTBR0.
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*/
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if (domain->mmu->features->twobit_imttbcr_sl0)
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tmp = IMTTBCR_SL0_TWOBIT_LVL_1;
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else
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tmp = IMTTBCR_SL0_LVL_1;
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ipmmu_ctx_write_root(domain, IMTTBCR, IMTTBCR_EAE |
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IMTTBCR_SH0_INNER_SHAREABLE | IMTTBCR_ORGN0_WB_WA |
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IMTTBCR_IRGN0_WB_WA | IMTTBCR_SL0_LVL_1);
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IMTTBCR_IRGN0_WB_WA | tmp);
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/* MAIR0 */
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ipmmu_ctx_write_root(domain, IMMAIR0,
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@ -889,6 +900,7 @@ static const struct ipmmu_features ipmmu_features_default = {
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.has_cache_leaf_nodes = false,
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.number_of_contexts = 1, /* software only tested with one context */
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.setup_imbuscr = true,
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.twobit_imttbcr_sl0 = false,
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};
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static const struct of_device_id ipmmu_of_ids[] = {
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