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mwl8k: remove various unused struct members and defines
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
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22e66a4c15
commit
c23b5a6994
@ -58,7 +58,6 @@ MODULE_DEVICE_TABLE(pci, mwl8k_table);
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#define MWL8K_HIU_H2A_INTERRUPT_STATUS_MASK 0x00000c28
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#define MWL8K_H2A_INT_DUMMY (1 << 20)
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#define MWL8K_H2A_INT_RESET (1 << 15)
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#define MWL8K_H2A_INT_PS (1 << 2)
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#define MWL8K_H2A_INT_DOORBELL (1 << 1)
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#define MWL8K_H2A_INT_PPA_READY (1 << 0)
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@ -161,10 +160,8 @@ struct mwl8k_priv {
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/* lock held over TX and TX reap */
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spinlock_t tx_lock;
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u32 int_mask;
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struct ieee80211_vif *vif;
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struct list_head vif_list;
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struct ieee80211_channel *current_channel;
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@ -173,10 +170,8 @@ struct mwl8k_priv {
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dma_addr_t cookie_dma;
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u16 num_mcaddrs;
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u16 region_code;
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u8 hw_rev;
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__le32 fw_rev;
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u32 wep_enabled;
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/*
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* Running count of TX packets in flight, to avoid
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@ -226,8 +221,6 @@ struct mwl8k_priv {
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/* Per interface specific private data */
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struct mwl8k_vif {
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struct list_head node;
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/* backpointer to parent config block */
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struct mwl8k_priv *priv;
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@ -247,18 +240,11 @@ struct mwl8k_vif {
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/* number of supported legacy rates */
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u8 legacy_nrates;
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/* Number of supported MCS rates. Work in progress */
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u8 mcs_nrates;
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/* Index into station database.Returned by update_sta_db call */
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u8 peer_id;
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/* Non AMPDU sequence number assigned by driver */
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u16 seqno;
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/* Note:There is no channel info,
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* refer to the master channel info in priv
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*/
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};
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#define MWL8K_VIF(_vif) ((struct mwl8k_vif *)&((_vif)->drv_priv))
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@ -681,11 +667,9 @@ struct ewc_ht_info {
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/* Peer Entry flags - used to define the type of the peer node */
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#define MWL8K_PEER_TYPE_ACCESSPOINT 2
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#define MWL8K_PEER_TYPE_ADHOC_STATION 4
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#define MWL8K_IEEE_LEGACY_DATA_RATES 12
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#define MWL8K_MCS_BITMAP_SIZE 16
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#define pad_size 16
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struct peer_capability_info {
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/* Peer type - AP vs. STA. */
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@ -707,7 +691,7 @@ struct peer_capability_info {
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/* HT rate table. Intersection of our rates and peer rates. */
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__u8 ht_rates[MWL8K_MCS_BITMAP_SIZE];
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__u8 pad[pad_size];
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__u8 pad[16];
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/* If set, interoperability mode, no proprietary extensions. */
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__u8 interop;
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@ -717,15 +701,6 @@ struct peer_capability_info {
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} __attribute__((packed));
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/* Inline functions to manipulate QoS field in data descriptor. */
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static inline u16 mwl8k_qos_setbit_tid(u16 qos, u8 tid)
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{
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u16 val_mask = 0x000f;
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u16 qos_mask = ~val_mask;
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/* TID bits 0-3 */
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return (qos & qos_mask) | (tid & val_mask);
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}
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static inline u16 mwl8k_qos_setbit_eosp(u16 qos)
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{
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u16 val_mask = 1 << 4;
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@ -826,9 +801,7 @@ static inline struct sk_buff *mwl8k_add_dma_header(struct sk_buff *skb)
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/*
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* Packet reception.
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*/
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#define MWL8K_RX_CTRL_KEY_INDEX_MASK 0x30
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#define MWL8K_RX_CTRL_OWNED_BY_HOST 0x02
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#define MWL8K_RX_CTRL_AMPDU 0x01
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struct mwl8k_rx_desc {
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__le16 pkt_len;
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@ -1073,8 +1046,6 @@ enum {
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/* Transmit packet ACK policy */
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#define MWL8K_TXD_ACK_POLICY_NORMAL 0
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#define MWL8K_TXD_ACK_POLICY_NONE 1
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#define MWL8K_TXD_ACK_POLICY_NO_EXPLICIT 2
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#define MWL8K_TXD_ACK_POLICY_BLOCKACK 3
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#define GET_TXQ(_ac) (\
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@ -1083,20 +1054,11 @@ enum {
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((_ac) == WME_AC_BK) ? MWL8K_WME_AC_BK : \
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MWL8K_WME_AC_BE)
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#define MWL8K_TXD_STATUS_IDLE 0x00000000
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#define MWL8K_TXD_STATUS_USED 0x00000001
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#define MWL8K_TXD_STATUS_OK 0x00000001
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#define MWL8K_TXD_STATUS_OK_RETRY 0x00000002
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#define MWL8K_TXD_STATUS_OK_MORE_RETRY 0x00000004
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#define MWL8K_TXD_STATUS_MULTICAST_TX 0x00000008
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#define MWL8K_TXD_STATUS_BROADCAST_TX 0x00000010
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#define MWL8K_TXD_STATUS_FAILED_LINK_ERROR 0x00000020
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#define MWL8K_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040
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#define MWL8K_TXD_STATUS_FAILED_AGING 0x00000080
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#define MWL8K_TXD_STATUS_HOST_CMD 0x40000000
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#define MWL8K_TXD_STATUS_FW_OWNED 0x80000000
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#define MWL8K_TXD_SOFTSTALE 0x80
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#define MWL8K_TXD_SOFTSTALE_MGMT_RETRY 0x01
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struct mwl8k_tx_desc {
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__le32 status;
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@ -1279,12 +1241,10 @@ static int mwl8k_tx_wait_empty(struct ieee80211_hw *hw, u32 delay_ms)
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return 0;
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}
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#define MWL8K_TXD_OK (MWL8K_TXD_STATUS_OK | \
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MWL8K_TXD_STATUS_OK_RETRY | \
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MWL8K_TXD_STATUS_OK_MORE_RETRY)
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#define MWL8K_TXD_SUCCESS(stat) ((stat) & MWL8K_TXD_OK)
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#define MWL8K_TXD_FAIL_RETRY(stat) \
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((stat) & (MWL8K_TXD_STATUS_FAILED_EXCEED_LIMIT))
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#define MWL8K_TXD_SUCCESS(status) \
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((status) & (MWL8K_TXD_STATUS_OK | \
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MWL8K_TXD_STATUS_OK_RETRY | \
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MWL8K_TXD_STATUS_OK_MORE_RETRY))
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static void mwl8k_txq_reclaim(struct ieee80211_hw *hw, int index, int force)
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{
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@ -1671,7 +1631,6 @@ static int mwl8k_cmd_get_hw_spec(struct ieee80211_hw *hw)
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priv->num_mcaddrs = le16_to_cpu(cmd->num_mcaddrs);
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priv->fw_rev = le32_to_cpu(cmd->fw_rev);
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priv->hw_rev = cmd->hw_rev;
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priv->region_code = le16_to_cpu(cmd->region_code);
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}
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kfree(cmd);
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@ -2150,7 +2109,6 @@ struct mwl8k_cmd_set_edca_params {
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__u8 txq;
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} __attribute__((packed));
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#define MWL8K_GET_EDCA_ALL 0
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#define MWL8K_SET_EDCA_CW 0x01
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#define MWL8K_SET_EDCA_TXOP 0x02
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#define MWL8K_SET_EDCA_AIFS 0x04
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@ -2323,18 +2281,12 @@ static int mwl8k_cmd_update_sta_db(struct ieee80211_hw *hw,
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/*
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* CMD_SET_AID.
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*/
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#define IEEE80211_OPMODE_DISABLED 0x00
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#define IEEE80211_OPMODE_NON_MEMBER_PROT_MODE 0x01
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#define IEEE80211_OPMODE_ONE_20MHZ_STA_PROT_MODE 0x02
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#define IEEE80211_OPMODE_HTMIXED_PROT_MODE 0x03
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#define MWL8K_RATE_INDEX_MAX_ARRAY 14
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#define MWL8K_FRAME_PROT_DISABLED 0x00
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#define MWL8K_FRAME_PROT_11G 0x07
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#define MWL8K_FRAME_PROT_11N_HT_40MHZ_ONLY 0x02
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#define MWL8K_FRAME_PROT_11N_HT_ALL 0x06
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#define MWL8K_FRAME_PROT_MASK 0x07
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struct mwl8k_cmd_update_set_aid {
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struct mwl8k_cmd_pkt header;
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@ -2439,10 +2391,6 @@ static int mwl8k_update_rateset(struct ieee80211_hw *hw,
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*/
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#define MWL8K_RATE_TABLE_SIZE 8
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#define MWL8K_UCAST_RATE 0
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#define MWL8K_MCAST_RATE 1
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#define MWL8K_BCAST_RATE 2
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#define MWL8K_USE_FIXED_RATE 0x0001
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#define MWL8K_USE_AUTO_RATE 0x0002
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struct mwl8k_rate_entry {
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@ -2535,7 +2483,6 @@ static irqreturn_t mwl8k_interrupt(int irq, void *dev_id)
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status = ioread32(priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
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iowrite32(~status, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
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status &= priv->int_mask;
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if (!status)
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return IRQ_NONE;
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@ -2873,7 +2820,7 @@ static int mwl8k_start(struct ieee80211_hw *hw)
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}
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/* Enable interrupts */
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iowrite32(priv->int_mask, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
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iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
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worker = kzalloc(sizeof(*worker), GFP_KERNEL);
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if (worker == NULL) {
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@ -3532,7 +3479,6 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
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priv->hostcmd_wait = NULL;
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priv->tx_wait = NULL;
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priv->inconfig = false;
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priv->wep_enabled = 0;
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priv->wmm_mode = false;
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priv->pending_tx_pkts = 0;
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strncpy(priv->name, MWL8K_NAME, sizeof(priv->name));
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@ -3614,8 +3560,7 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
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}
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iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS);
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priv->int_mask = 0;
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iowrite32(priv->int_mask, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
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iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
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iowrite32(0, priv->regs + MWL8K_HIU_A2H_INTERRUPT_CLEAR_SEL);
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iowrite32(0xffffffff, priv->regs + MWL8K_HIU_A2H_INTERRUPT_STATUS_MASK);
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@ -3652,9 +3597,7 @@ static int __devinit mwl8k_probe(struct pci_dev *pdev,
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* commands use interrupts and avoids polling. Disable
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* interrupts when done.
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*/
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priv->int_mask |= MWL8K_A2H_EVENTS;
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iowrite32(priv->int_mask, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
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iowrite32(MWL8K_A2H_EVENTS, priv->regs + MWL8K_HIU_A2H_INTERRUPT_MASK);
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/* Get config data, mac addrs etc */
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rc = mwl8k_cmd_get_hw_spec(hw);
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