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arm64: dts: renesas: r8a774c0: Fix SCIF5 DMA channels
Correct the DMA channels for SCIF5 from 16..47 to 0..15, as was done for
R-Car E3.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Fixes: 2660a6af69
("arm64: dts: renesas: r8a774c0: Add SCIF and HSCIF nodes")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -2,7 +2,7 @@
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/*
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* Device Tree Source for the RZ/G2E (R8A774C0) SoC
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*
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* Copyright (C) 2018 Renesas Electronics Corp.
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* Copyright (C) 2018-2019 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
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@ -990,9 +990,8 @@
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<&cpg CPG_CORE R8A774C0_CLK_S3D1C>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
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<&dmac2 0x5b>, <&dmac2 0x5a>;
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dma-names = "tx", "rx", "tx", "rx";
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dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
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dma-names = "tx", "rx";
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power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
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resets = <&cpg 202>;
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status = "disabled";
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