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x86: integrate 32-bit and 64-bit code in msr.h
This patches proceeds with the integration of msr.h, making the code unified, instead of having a version for each architecture. We stick with the native_* functions, and then paravirt comes for free. Signed-off-by: Glauber de Oliveira Costa <gcosta@redhat.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Glauber de Oliveira Costa
Ingo Molnar
parent
56ec1ddcff
commit
c210d24986
@ -9,6 +9,10 @@
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/asm.h>
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#include <asm/errno.h>
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static inline unsigned long long native_read_tscp(int *aux)
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{
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unsigned long low, high;
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@ -17,37 +21,36 @@ static inline unsigned long long native_read_tscp(int *aux)
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return low | ((u64)high >> 32);
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}
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#define rdtscp(low, high, aux) \
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do { \
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unsigned long long _val = native_read_tscp(&(aux)); \
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(low) = (u32)_val; \
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(high) = (u32)(_val >> 32); \
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} while (0)
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#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
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/*
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* i386 calling convention returns 64-bit value in edx:eax, while
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* x86_64 returns at rax. Also, the "A" constraint does not really
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* mean rdx:rax in x86_64, so we need specialized behaviour for each
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* architecture
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*/
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#ifdef CONFIG_X86_64
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#define DECLARE_ARGS(val, low, high) unsigned low, high
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#define EAX_EDX_VAL(val, low, high) (low | ((u64)(high) << 32))
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#define EAX_EDX_ARGS(val, low, high) "a" (low), "d" (high)
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#define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high)
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#else
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#define DECLARE_ARGS(val, low, high) unsigned long long val
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#define EAX_EDX_VAL(val, low, high) (val)
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#define EAX_EDX_ARGS(val, low, high) "A" (val)
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#define EAX_EDX_RET(val, low, high) "=A" (val)
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#endif
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#endif
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#ifdef __i386__
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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#include <asm/asm.h>
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#include <asm/errno.h>
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static inline unsigned long long native_read_msr(unsigned int msr)
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{
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unsigned long long val;
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DECLARE_ARGS(val, low, high);
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asm volatile("rdmsr" : "=A" (val) : "c" (msr));
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return val;
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asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr));
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return EAX_EDX_VAL(val, low, high);
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}
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static inline unsigned long long native_read_msr_safe(unsigned int msr,
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int *err)
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{
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unsigned long long val;
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DECLARE_ARGS(val, low, high);
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asm volatile("2: rdmsr ; xor %0,%0\n"
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"1:\n\t"
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@ -58,10 +61,9 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
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_ASM_ALIGN "\n\t"
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_ASM_PTR " 2b,3b\n\t"
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".previous"
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: "=r" (*err), "=A" (val)
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: "=r" (*err), EAX_EDX_RET(val, low, high)
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: "c" (msr), "i" (-EFAULT));
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return val;
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return EAX_EDX_VAL(val, low, high);
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}
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static inline void native_write_msr(unsigned int msr,
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@ -91,16 +93,18 @@ static inline int native_write_msr_safe(unsigned int msr,
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static inline unsigned long long native_read_tsc(void)
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{
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unsigned long long val;
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asm volatile("rdtsc" : "=A" (val));
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return val;
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DECLARE_ARGS(val, low, high);
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asm volatile("rdtsc" : EAX_EDX_RET(val, low, high));
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return EAX_EDX_VAL(val, low, high);
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}
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static inline unsigned long long native_read_pmc(int counter)
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{
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unsigned long long val;
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asm volatile("rdpmc" : "=A" (val) : "c" (counter));
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return val;
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DECLARE_ARGS(val, low, high);
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asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter));
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return EAX_EDX_VAL(val, low, high);
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}
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#ifdef CONFIG_PARAVIRT
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@ -128,7 +132,8 @@ static inline void wrmsr(unsigned msr, unsigned low, unsigned high)
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#define rdmsrl(msr,val) \
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((val) = native_read_msr(msr))
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#define wrmsrl(msr, val) native_write_msr(msr, (u32)val, (u32)(val >> 32))
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#define wrmsrl(msr, val) \
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native_write_msr(msr, (u32)((u64)(val)), (u32)((u64)(val) >> 32))
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/* wrmsr with exception handling */
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static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
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@ -160,104 +165,25 @@ static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high)
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(low) = (u32)_l; \
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(high) = (u32)(_l >> 32); \
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} while(0)
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#define rdtscp(low, high, aux) \
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do { \
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unsigned long long _val = native_read_tscp(&(aux)); \
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(low) = (u32)_val; \
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(high) = (u32)(_val >> 32); \
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} while (0)
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#define rdtscpll(val, aux) (val) = native_read_tscp(&(aux))
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#endif /* !CONFIG_PARAVIRT */
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#endif /* ! __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#else /* __i386__ */
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#ifndef __ASSEMBLY__
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#include <linux/errno.h>
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/*
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* Access to machine-specific registers (available on 586 and better only)
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* Note: the rd* operations modify the parameters directly (without using
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* pointer indirection), this allows gcc to optimize better
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*/
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#define rdmsr(msr,val1,val2) \
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__asm__ __volatile__("rdmsr" \
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: "=a" (val1), "=d" (val2) \
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: "c" (msr))
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#define rdmsrl(msr,val) do { unsigned long a__,b__; \
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__asm__ __volatile__("rdmsr" \
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: "=a" (a__), "=d" (b__) \
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: "c" (msr)); \
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val = a__ | (b__<<32); \
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} while(0)
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#define wrmsr(msr,val1,val2) \
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__asm__ __volatile__("wrmsr" \
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: /* no outputs */ \
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: "c" (msr), "a" (val1), "d" (val2))
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#define wrmsrl(msr,val) wrmsr(msr,(__u32)((__u64)(val)),((__u64)(val))>>32)
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#define rdtsc(low,high) \
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__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
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#define rdtscl(low) \
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__asm__ __volatile__ ("rdtsc" : "=a" (low) : : "edx")
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#define rdtscll(val) do { \
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unsigned int __a,__d; \
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__asm__ __volatile__("rdtsc" : "=a" (__a), "=d" (__d)); \
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(val) = ((unsigned long)__a) | (((unsigned long)__d)<<32); \
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} while(0)
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#define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
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#define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
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#define write_rdtscp_aux(val) wrmsr(0xc0000103, val, 0)
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#define rdpmc(counter,low,high) \
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__asm__ __volatile__("rdpmc" \
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: "=a" (low), "=d" (high) \
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: "c" (counter))
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#ifdef __KERNEL__
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/* wrmsr with exception handling */
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#define wrmsr_safe(msr,a,b) ({ int ret__; \
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asm volatile("2: wrmsr ; xorl %0,%0\n" \
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"1:\n\t" \
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".section .fixup,\"ax\"\n\t" \
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"3: movl %4,%0 ; jmp 1b\n\t" \
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".previous\n\t" \
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".section __ex_table,\"a\"\n" \
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" .align 8\n\t" \
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" .quad 2b,3b\n\t" \
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".previous" \
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: "=a" (ret__) \
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: "c" (msr), "0" (a), "d" (b), "i" (-EFAULT)); \
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ret__; })
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#define checking_wrmsrl(msr,val) wrmsr_safe(msr,(u32)(val),(u32)((val)>>32))
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#define rdmsr_safe(msr,a,b) \
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({ int ret__; \
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asm volatile ("1: rdmsr\n" \
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"2:\n" \
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".section .fixup,\"ax\"\n" \
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"3: movl %4,%0\n" \
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" jmp 2b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n" \
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" .align 8\n" \
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" .quad 1b,3b\n" \
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".previous":"=&bDS" (ret__), "=a"(*(a)), "=d"(*(b)) \
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:"c"(msr), "i"(-EIO), "0"(0)); \
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ret__; })
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#endif /* __ASSEMBLY__ */
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#endif /* !__i386__ */
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_SMP
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void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
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void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
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@ -281,7 +207,8 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
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return wrmsr_safe(msr_no, l, h);
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}
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#endif /* CONFIG_SMP */
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#endif /* __KERNEL__ */
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif
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