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Merge branch 'topic/qcom' into for-linus
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commit
c203f677c0
@ -47,8 +47,8 @@ When the OS is not in control of the management interface (i.e. it's a guest),
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the channel nodes appear on their own, not under a management node.
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Required properties:
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- compatible: must contain "qcom,hidma-1.0" for initial HW or "qcom,hidma-1.1"
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for MSI capable HW.
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- compatible: must contain "qcom,hidma-1.0" for initial HW or
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"qcom,hidma-1.1"/"qcom,hidma-1.2" for MSI capable HW.
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- reg: Addresses for the transfer and event channel
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- interrupts: Should contain the event interrupt
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- desc-count: Number of asynchronous requests this channel can handle
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@ -50,6 +50,7 @@
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/of_dma.h>
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#include <linux/of_device.h>
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#include <linux/property.h>
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#include <linux/delay.h>
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#include <linux/acpi.h>
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@ -104,6 +105,10 @@ static unsigned int nr_desc_prm;
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module_param(nr_desc_prm, uint, 0644);
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MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)");
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enum hidma_cap {
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HIDMA_MSI_CAP = 1,
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HIDMA_IDENTITY_CAP,
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};
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/* process completed descriptors */
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static void hidma_process_completed(struct hidma_chan *mchan)
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@ -736,25 +741,12 @@ static int hidma_request_msi(struct hidma_dev *dmadev,
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#endif
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}
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static bool hidma_msi_capable(struct device *dev)
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static bool hidma_test_capability(struct device *dev, enum hidma_cap test_cap)
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{
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struct acpi_device *adev = ACPI_COMPANION(dev);
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const char *of_compat;
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int ret = -EINVAL;
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enum hidma_cap cap;
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if (!adev || acpi_disabled) {
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ret = device_property_read_string(dev, "compatible",
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&of_compat);
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if (ret)
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return false;
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ret = strcmp(of_compat, "qcom,hidma-1.1");
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} else {
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#ifdef CONFIG_ACPI
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ret = strcmp(acpi_device_hid(adev), "QCOM8062");
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#endif
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}
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return ret == 0;
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cap = (enum hidma_cap) device_get_match_data(dev);
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return cap ? ((cap & test_cap) > 0) : 0;
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}
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static int hidma_probe(struct platform_device *pdev)
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@ -834,8 +826,7 @@ static int hidma_probe(struct platform_device *pdev)
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* Determine the MSI capability of the platform. Old HW doesn't
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* support MSI.
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*/
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msi = hidma_msi_capable(&pdev->dev);
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msi = hidma_test_capability(&pdev->dev, HIDMA_MSI_CAP);
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device_property_read_u32(&pdev->dev, "desc-count",
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&dmadev->nr_descriptors);
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@ -848,7 +839,10 @@ static int hidma_probe(struct platform_device *pdev)
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if (!dmadev->nr_descriptors)
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dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC;
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dmadev->chidx = readl(dmadev->dev_trca + 0x28);
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if (hidma_test_capability(&pdev->dev, HIDMA_IDENTITY_CAP))
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dmadev->chidx = readl(dmadev->dev_trca + 0x40);
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else
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dmadev->chidx = readl(dmadev->dev_trca + 0x28);
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/* Set DMA mask to 64 bits. */
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rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
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@ -953,7 +947,8 @@ static int hidma_remove(struct platform_device *pdev)
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#if IS_ENABLED(CONFIG_ACPI)
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static const struct acpi_device_id hidma_acpi_ids[] = {
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{"QCOM8061"},
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{"QCOM8062"},
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{"QCOM8062", HIDMA_MSI_CAP},
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{"QCOM8063", (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP)},
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{},
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};
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MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids);
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@ -961,7 +956,9 @@ MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids);
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static const struct of_device_id hidma_match[] = {
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{.compatible = "qcom,hidma-1.0",},
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{.compatible = "qcom,hidma-1.1",},
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{.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),},
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{.compatible = "qcom,hidma-1.2",
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.data = (void *)(HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP),},
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{},
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};
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MODULE_DEVICE_TABLE(of, hidma_match);
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@ -393,6 +393,8 @@ static int hidma_ll_reset(struct hidma_lldev *lldev)
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*/
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static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause)
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{
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unsigned long irqflags;
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if (cause & HIDMA_ERR_INT_MASK) {
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dev_err(lldev->dev, "error 0x%x, disabling...\n",
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cause);
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@ -410,6 +412,10 @@ static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause)
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return;
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}
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spin_lock_irqsave(&lldev->lock, irqflags);
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writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
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spin_unlock_irqrestore(&lldev->lock, irqflags);
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/*
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* Fine tuned for this HW...
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*
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@ -421,9 +427,6 @@ static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause)
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* Try to consume as many EVREs as possible.
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*/
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hidma_handle_tre_completion(lldev);
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/* We consumed TREs or there are pending TREs or EVREs. */
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writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
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}
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irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
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