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MIPS: Ingenic: Add CPU nodes for Ingenic SoCs.

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Add 'cpus' node to the jz4725b.dtsi, jz4740.dtsi, jz4770.dtsi,
jz4780.dtsi, x1000.dtsi, and x1830.dtsi files.

Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
Tested-by: Paul Boddie <paul@boddie.org.uk>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
周琰杰 (Zhou Yanjie) 2020-09-19 19:38:59 +08:00 committed by Thomas Bogendoerfer
parent 307c992639
commit c1f6b45e63
6 changed files with 93 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
arch/mips/boot/dts/ingenic/jz4725b.dtsi
View File

@ -7,6 +7,20 @@
#size-cells = <1>;
compatible = "ingenic,jz4725b";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-mxu1.0";
reg = <0>;
clocks = <&cgu JZ4725B_CLK_CCLK>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;

14
arch/mips/boot/dts/ingenic/jz4740.dtsi
View File

@ -7,6 +7,20 @@
#size-cells = <1>;
compatible = "ingenic,jz4740";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-mxu1.0";
reg = <0>;
clocks = <&cgu JZ4740_CLK_CCLK>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;

15
arch/mips/boot/dts/ingenic/jz4770.dtsi
View File

@ -1,5 +1,4 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/clock/jz4770-cgu.h>
#include <dt-bindings/clock/ingenic,tcu.h>
@ -8,6 +7,20 @@
#size-cells = <1>;
compatible = "ingenic,jz4770";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu JZ4770_CLK_CCLK>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;

23
arch/mips/boot/dts/ingenic/jz4780.dtsi
View File

@ -8,6 +8,29 @@
#size-cells = <1>;
compatible = "ingenic,jz4780";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu JZ4780_CLK_CPU>;
clock-names = "cpu";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <1>;
clocks = <&cgu JZ4780_CLK_CORE1>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;

14
arch/mips/boot/dts/ingenic/x1000.dtsi
View File

@ -8,6 +8,20 @@
#size-cells = <1>;
compatible = "ingenic,x1000", "ingenic,x1000e";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu1.0-mxu1.1";
reg = <0>;
clocks = <&cgu X1000_CLK_CPU>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;

14
arch/mips/boot/dts/ingenic/x1830.dtsi
View File

@ -8,6 +8,20 @@
#size-cells = <1>;
compatible = "ingenic,x1830";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "ingenic,xburst-fpu2.0-mxu2.0";
reg = <0>;
clocks = <&cgu X1830_CLK_CPU>;
clock-names = "cpu";
};
};
cpuintc: interrupt-controller {
#address-cells = <0>;
#interrupt-cells = <1>;