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net: aquantia: Ethtool based ring size configuration
Implemented ring size setup, min/max validation and reconfiguration in runtime. Signed-off-by: Anton Mikaev <amikaev@aquantia.com> Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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c18a9c0966
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c1af542795
@ -11,6 +11,7 @@
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#include "aq_ethtool.h"
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#include "aq_ethtool.h"
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#include "aq_nic.h"
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#include "aq_nic.h"
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#include "aq_vec.h"
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static void aq_ethtool_get_regs(struct net_device *ndev,
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static void aq_ethtool_get_regs(struct net_device *ndev,
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struct ethtool_regs *regs, void *p)
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struct ethtool_regs *regs, void *p)
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@ -284,6 +285,64 @@ static int aq_ethtool_set_coalesce(struct net_device *ndev,
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return aq_nic_update_interrupt_moderation_settings(aq_nic);
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return aq_nic_update_interrupt_moderation_settings(aq_nic);
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}
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}
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static void aq_get_ringparam(struct net_device *ndev,
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struct ethtool_ringparam *ring)
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{
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struct aq_nic_s *aq_nic = netdev_priv(ndev);
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struct aq_nic_cfg_s *aq_nic_cfg = aq_nic_get_cfg(aq_nic);
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ring->rx_pending = aq_nic_cfg->rxds;
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ring->tx_pending = aq_nic_cfg->txds;
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ring->rx_max_pending = aq_nic_cfg->aq_hw_caps->rxds_max;
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ring->tx_max_pending = aq_nic_cfg->aq_hw_caps->txds_max;
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}
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static int aq_set_ringparam(struct net_device *ndev,
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struct ethtool_ringparam *ring)
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{
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int err = 0;
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bool ndev_running = false;
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struct aq_nic_s *aq_nic = netdev_priv(ndev);
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struct aq_nic_cfg_s *aq_nic_cfg = aq_nic_get_cfg(aq_nic);
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const struct aq_hw_caps_s *hw_caps = aq_nic_cfg->aq_hw_caps;
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if (ring->rx_mini_pending || ring->rx_jumbo_pending) {
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err = -EOPNOTSUPP;
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goto err_exit;
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}
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if (netif_running(ndev)) {
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ndev_running = true;
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dev_close(ndev);
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}
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aq_nic_free_vectors(aq_nic);
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aq_nic_cfg->rxds = max(ring->rx_pending, hw_caps->rxds_min);
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aq_nic_cfg->rxds = min(aq_nic_cfg->rxds, hw_caps->rxds_max);
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aq_nic_cfg->rxds = ALIGN(aq_nic_cfg->rxds, AQ_HW_RXD_MULTIPLE);
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aq_nic_cfg->txds = max(ring->tx_pending, hw_caps->txds_min);
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aq_nic_cfg->txds = min(aq_nic_cfg->txds, hw_caps->txds_max);
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aq_nic_cfg->txds = ALIGN(aq_nic_cfg->txds, AQ_HW_TXD_MULTIPLE);
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for (aq_nic->aq_vecs = 0; aq_nic->aq_vecs < aq_nic_cfg->vecs;
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aq_nic->aq_vecs++) {
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aq_nic->aq_vec[aq_nic->aq_vecs] =
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aq_vec_alloc(aq_nic, aq_nic->aq_vecs, aq_nic_cfg);
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if (unlikely(!aq_nic->aq_vec[aq_nic->aq_vecs])) {
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err = -ENOMEM;
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goto err_exit;
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}
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}
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if (ndev_running)
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err = dev_open(ndev);
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err_exit:
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return err;
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}
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const struct ethtool_ops aq_ethtool_ops = {
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const struct ethtool_ops aq_ethtool_ops = {
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.get_link = aq_ethtool_get_link,
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.get_link = aq_ethtool_get_link,
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.get_regs_len = aq_ethtool_get_regs_len,
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.get_regs_len = aq_ethtool_get_regs_len,
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@ -291,6 +350,8 @@ const struct ethtool_ops aq_ethtool_ops = {
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.get_drvinfo = aq_ethtool_get_drvinfo,
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.get_drvinfo = aq_ethtool_get_drvinfo,
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.get_strings = aq_ethtool_get_strings,
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.get_strings = aq_ethtool_get_strings,
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.get_rxfh_indir_size = aq_ethtool_get_rss_indir_size,
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.get_rxfh_indir_size = aq_ethtool_get_rss_indir_size,
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.get_ringparam = aq_get_ringparam,
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.set_ringparam = aq_set_ringparam,
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.get_rxfh_key_size = aq_ethtool_get_rss_key_size,
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.get_rxfh_key_size = aq_ethtool_get_rss_key_size,
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.get_rxfh = aq_ethtool_get_rss,
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.get_rxfh = aq_ethtool_get_rss,
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.get_rxnfc = aq_ethtool_get_rxnfc,
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.get_rxnfc = aq_ethtool_get_rxnfc,
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@ -24,8 +24,10 @@ struct aq_hw_caps_s {
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u64 link_speed_msk;
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u64 link_speed_msk;
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unsigned int hw_priv_flags;
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unsigned int hw_priv_flags;
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u32 media_type;
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u32 media_type;
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u32 rxds;
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u32 rxds_max;
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u32 txds;
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u32 txds_max;
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u32 rxds_min;
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u32 txds_min;
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u32 txhwb_alignment;
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u32 txhwb_alignment;
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u32 irq_mask;
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u32 irq_mask;
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u32 vecs;
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u32 vecs;
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@ -98,6 +100,9 @@ struct aq_stats_s {
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#define AQ_HW_MEDIA_TYPE_TP 1U
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#define AQ_HW_MEDIA_TYPE_TP 1U
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#define AQ_HW_MEDIA_TYPE_FIBRE 2U
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#define AQ_HW_MEDIA_TYPE_FIBRE 2U
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#define AQ_HW_TXD_MULTIPLE 8U
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#define AQ_HW_RXD_MULTIPLE 8U
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struct aq_hw_s {
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struct aq_hw_s {
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atomic_t flags;
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atomic_t flags;
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u8 rbl_enabled:1;
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u8 rbl_enabled:1;
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@ -89,8 +89,8 @@ void aq_nic_cfg_start(struct aq_nic_s *self)
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aq_nic_rss_init(self, cfg->num_rss_queues);
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aq_nic_rss_init(self, cfg->num_rss_queues);
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/*descriptors */
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/*descriptors */
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cfg->rxds = min(cfg->aq_hw_caps->rxds, AQ_CFG_RXDS_DEF);
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cfg->rxds = min(cfg->aq_hw_caps->rxds_max, AQ_CFG_RXDS_DEF);
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cfg->txds = min(cfg->aq_hw_caps->txds, AQ_CFG_TXDS_DEF);
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cfg->txds = min(cfg->aq_hw_caps->txds_max, AQ_CFG_TXDS_DEF);
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/*rss rings */
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/*rss rings */
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cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF);
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cfg->vecs = min(cfg->aq_hw_caps->vecs, AQ_CFG_VECS_DEF);
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@ -19,29 +19,31 @@
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#include "hw_atl_a0_internal.h"
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#include "hw_atl_a0_internal.h"
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#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \
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#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \
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.is_64_dma = true, \
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.is_64_dma = true, \
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.msix_irqs = 4U, \
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.msix_irqs = 4U, \
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.irq_mask = ~0U, \
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.irq_mask = ~0U, \
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.vecs = HW_ATL_A0_RSS_MAX, \
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.vecs = HW_ATL_A0_RSS_MAX, \
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.tcs = HW_ATL_A0_TC_MAX, \
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.tcs = HW_ATL_A0_TC_MAX, \
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.rxd_alignment = 1U, \
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.rxd_alignment = 1U, \
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.rxd_size = HW_ATL_A0_RXD_SIZE, \
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.rxd_size = HW_ATL_A0_RXD_SIZE, \
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.rxds = 248U, \
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.rxds_max = HW_ATL_A0_MAX_RXD, \
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.txd_alignment = 1U, \
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.rxds_min = HW_ATL_A0_MIN_RXD, \
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.txd_size = HW_ATL_A0_TXD_SIZE, \
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.txd_alignment = 1U, \
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.txds = 8U * 1024U, \
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.txd_size = HW_ATL_A0_TXD_SIZE, \
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.txhwb_alignment = 4096U, \
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.txds_max = HW_ATL_A0_MAX_TXD, \
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.tx_rings = HW_ATL_A0_TX_RINGS, \
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.txds_min = HW_ATL_A0_MIN_RXD, \
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.rx_rings = HW_ATL_A0_RX_RINGS, \
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.txhwb_alignment = 4096U, \
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.hw_features = NETIF_F_HW_CSUM | \
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.tx_rings = HW_ATL_A0_TX_RINGS, \
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NETIF_F_RXHASH | \
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.rx_rings = HW_ATL_A0_RX_RINGS, \
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NETIF_F_RXCSUM | \
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.hw_features = NETIF_F_HW_CSUM | \
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NETIF_F_SG | \
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NETIF_F_RXHASH | \
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NETIF_F_TSO, \
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NETIF_F_RXCSUM | \
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NETIF_F_SG | \
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NETIF_F_TSO, \
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.hw_priv_flags = IFF_UNICAST_FLT, \
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.hw_priv_flags = IFF_UNICAST_FLT, \
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.flow_control = true, \
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.flow_control = true, \
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.mtu = HW_ATL_A0_MTU_JUMBO, \
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.mtu = HW_ATL_A0_MTU_JUMBO, \
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.mac_regs_count = 88, \
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.mac_regs_count = 88, \
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.hw_alive_check_addr = 0x10U
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.hw_alive_check_addr = 0x10U
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const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
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const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
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@ -88,4 +88,12 @@
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#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
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#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
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#define HW_ATL_A0_MIN_RXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE))
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#define HW_ATL_A0_MIN_TXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE))
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#define HW_ATL_A0_MAX_RXD 8184U
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#define HW_ATL_A0_MAX_TXD 8184U
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#endif /* HW_ATL_A0_INTERNAL_H */
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#endif /* HW_ATL_A0_INTERNAL_H */
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#include "hw_atl_llh_internal.h"
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#include "hw_atl_llh_internal.h"
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#define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
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#define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
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.is_64_dma = true, \
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.is_64_dma = true, \
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.msix_irqs = 4U, \
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.msix_irqs = 4U, \
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.irq_mask = ~0U, \
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.irq_mask = ~0U, \
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.vecs = HW_ATL_B0_RSS_MAX, \
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.vecs = HW_ATL_B0_RSS_MAX, \
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.tcs = HW_ATL_B0_TC_MAX, \
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.tcs = HW_ATL_B0_TC_MAX, \
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.rxd_alignment = 1U, \
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.rxd_alignment = 1U, \
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.rxd_size = HW_ATL_B0_RXD_SIZE, \
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.rxd_size = HW_ATL_B0_RXD_SIZE, \
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.rxds = 4U * 1024U, \
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.rxds_max = HW_ATL_B0_MAX_RXD, \
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.txd_alignment = 1U, \
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.rxds_min = HW_ATL_B0_MIN_RXD, \
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.txd_size = HW_ATL_B0_TXD_SIZE, \
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.txd_alignment = 1U, \
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.txds = 8U * 1024U, \
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.txd_size = HW_ATL_B0_TXD_SIZE, \
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.txhwb_alignment = 4096U, \
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.txds_max = HW_ATL_B0_MAX_TXD, \
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.tx_rings = HW_ATL_B0_TX_RINGS, \
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.txds_min = HW_ATL_B0_MIN_TXD, \
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.rx_rings = HW_ATL_B0_RX_RINGS, \
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.txhwb_alignment = 4096U, \
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.hw_features = NETIF_F_HW_CSUM | \
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.tx_rings = HW_ATL_B0_TX_RINGS, \
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NETIF_F_RXCSUM | \
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.rx_rings = HW_ATL_B0_RX_RINGS, \
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NETIF_F_RXHASH | \
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.hw_features = NETIF_F_HW_CSUM | \
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NETIF_F_SG | \
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NETIF_F_RXCSUM | \
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NETIF_F_TSO | \
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NETIF_F_RXHASH | \
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NETIF_F_LRO, \
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NETIF_F_SG | \
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.hw_priv_flags = IFF_UNICAST_FLT, \
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NETIF_F_TSO | \
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.flow_control = true, \
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NETIF_F_LRO, \
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.mtu = HW_ATL_B0_MTU_JUMBO, \
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.hw_priv_flags = IFF_UNICAST_FLT, \
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.mac_regs_count = 88, \
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.flow_control = true, \
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.mtu = HW_ATL_B0_MTU_JUMBO, \
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.mac_regs_count = 88, \
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.hw_alive_check_addr = 0x10U
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.hw_alive_check_addr = 0x10U
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const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
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const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
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#define HW_ATL_INTR_MODER_MAX 0x1FF
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#define HW_ATL_INTR_MODER_MAX 0x1FF
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#define HW_ATL_INTR_MODER_MIN 0xFF
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#define HW_ATL_INTR_MODER_MIN 0xFF
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#define HW_ATL_B0_MIN_RXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_RXD_MULTIPLE))
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#define HW_ATL_B0_MIN_TXD \
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(ALIGN(AQ_CFG_SKB_FRAGS_MAX + 1U, AQ_HW_TXD_MULTIPLE))
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#define HW_ATL_B0_MAX_RXD 8184U
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#define HW_ATL_B0_MAX_TXD 8184U
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/* HW layer capabilities */
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/* HW layer capabilities */
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#endif /* HW_ATL_B0_INTERNAL_H */
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#endif /* HW_ATL_B0_INTERNAL_H */
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