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MIPS: csrc-r4k: Refine rating computation

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Increase frequency addend dividend to 10000000 (10MHz) to
reasonably accommodate multi GHz level mips_hpt_frequency.

Cap rating of csrc-r4k into 299 to ensure it doesn't go into
"Desired" range, given all the drama we have with CP0 count
registers (SMP sync, behaviour on wait etc).

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Jiaxun Yang 2024-06-12 09:54:28 +01:00 committed by Thomas Bogendoerfer
parent 04f38d1a4d
commit c171186c17
1 changed files with 2 additions and 1 deletions
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3
arch/mips/kernel/csrc-r4k.c
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@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void)
return -ENXIO;
/* Calculate a somewhat reasonable rating value */
clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
clocksource_mips.rating = 200;
clocksource_mips.rating += clamp(mips_hpt_frequency / 10000000, 0, 99);
/*
* R2 onwards makes the count accessible to user mode so it can be used