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serial: 8250_dw: Revert "Improve clock rate setting"

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The commit

  de9e33bdfa ("serial: 8250_dw: Improve clock rate setting")

obviously tries to cure symptoms, and not a root cause.

The root cause is the non-flexible rate calculation inside the
corresponding clock driver. What we need is to provide maximum UART
divisor value to the clock driver to allow it do the job transparently
to the caller.

Since from the initial commit message I have got no clue which clock
driver actually needs to be amended, I leave this exercise to the people
who know better the case.

Moreover, it seems [1] the fix introduced a regression. And possible
even one more [2].

Taking above, revert the commit de9e33bdfa for now.

[1]: https://www.spinics.net/lists/linux-serial/msg28872.html
[2]: https://github.com/Dunedan/mbp-2016-linux/issues/29#issuecomment-357583782

Fixes: de9e33bdfa ("serial: 8250_dw: Improve clock rate setting")
Cc: stable <stable@vger.kernel.org> # 4.15
Cc: Ed Blake <ed.blake@sondrel.com>
Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Cc: Lukas Wunner <lukas@wunner.de>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Andy Shevchenko 2018-01-19 18:02:05 +02:00 committed by Greg Kroah-Hartman
parent a0075d168a
commit c14b65feac
1 changed files with 12 additions and 18 deletions
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30
drivers/tty/serial/8250/8250_dw.c
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@ -252,31 +252,25 @@ static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
struct ktermios *old)
{
unsigned int baud = tty_termios_baud_rate(termios);
unsigned int target_rate, min_rate, max_rate;
struct dw8250_data *d = p->private_data;
long rate;
int i, ret;
int ret;
if (IS_ERR(d->clk) || !old)
goto out;
/* Find a clk rate within +/-1.6% of an integer multiple of baudx16 */
target_rate = baud * 16;
min_rate = target_rate - (target_rate >> 6);
max_rate = target_rate + (target_rate >> 6);
for (i = 1; i <= UART_DIV_MAX; i++) {
rate = clk_round_rate(d->clk, i * target_rate);
if (rate >= i * min_rate && rate <= i * max_rate)
break;
}
if (i <= UART_DIV_MAX) {
clk_disable_unprepare(d->clk);
clk_disable_unprepare(d->clk);
rate = clk_round_rate(d->clk, baud * 16);
if (rate < 0)
ret = rate;
else if (rate == 0)
ret = -ENOENT;
else
ret = clk_set_rate(d->clk, rate);
clk_prepare_enable(d->clk);
if (!ret)
p->uartclk = rate;
}
clk_prepare_enable(d->clk);
if (!ret)
p->uartclk = rate;
out:
p->status &= ~UPSTAT_AUTOCTS;