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IB/hfi1: Build TID RDMA WRITE request

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This patch adds the functions to build TID RDMA WRITE request.
The work request opcode, packet opcode, and packet formats for TID
RDMA WRITE protocol are also defined in this patch.

Signed-off-by: Mitko Haralanov <mitko.haralanov@intel.com>
Signed-off-by: Mike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Kaike Wan <kaike.wan@intel.com>
Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Kaike Wan 2019-01-23 21:48:28 -08:00 committed by Doug Ledford
parent a2f3bde881
commit c098bbb00c
5 changed files with 104 additions and 0 deletions
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2
drivers/infiniband/hw/hfi1/qp.h
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@ -64,12 +64,14 @@ extern const struct rvt_operation_params hfi1_post_parms[];
* HFI1_S_AHG_CLEAR - have send engine clear ahg state * HFI1_S_AHG_CLEAR - have send engine clear ahg state
* HFI1_S_WAIT_PIO_DRAIN - qp waiting for PIOs to drain * HFI1_S_WAIT_PIO_DRAIN - qp waiting for PIOs to drain
* HFI1_S_WAIT_TID_SPACE - a QP is waiting for TID resource * HFI1_S_WAIT_TID_SPACE - a QP is waiting for TID resource
* HFI1_S_WAIT_TID_RESP - waiting for a TID RDMA WRITE response
* HFI1_S_MIN_BIT_MASK - the lowest bit that can be used by hfi1 * HFI1_S_MIN_BIT_MASK - the lowest bit that can be used by hfi1
*/ */
#define HFI1_S_AHG_VALID 0x80000000 #define HFI1_S_AHG_VALID 0x80000000
#define HFI1_S_AHG_CLEAR 0x40000000 #define HFI1_S_AHG_CLEAR 0x40000000
#define HFI1_S_WAIT_PIO_DRAIN 0x20000000 #define HFI1_S_WAIT_PIO_DRAIN 0x20000000
#define HFI1_S_WAIT_TID_SPACE 0x10000000 #define HFI1_S_WAIT_TID_SPACE 0x10000000
#define HFI1_S_WAIT_TID_RESP 0x08000000
#define HFI1_S_MIN_BIT_MASK 0x01000000 #define HFI1_S_MIN_BIT_MASK 0x01000000
/* /*

38
drivers/infiniband/hw/hfi1/tid_rdma.c
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@ -2975,3 +2975,41 @@ void setup_tid_rdma_wqe(struct rvt_qp *qp, struct rvt_swqe *wqe)
exit: exit:
rcu_read_unlock(); rcu_read_unlock();
} }
/* TID RDMA WRITE functions */
u32 hfi1_build_tid_rdma_write_req(struct rvt_qp *qp, struct rvt_swqe *wqe,
struct ib_other_headers *ohdr,
u32 *bth1, u32 *bth2, u32 *len)
{
struct hfi1_qp_priv *qpriv = qp->priv;
struct tid_rdma_request *req = wqe_to_tid_req(wqe);
struct tid_rdma_params *remote;
rcu_read_lock();
remote = rcu_dereference(qpriv->tid_rdma.remote);
/*
* Set the number of flow to be used based on negotiated
* parameters.
*/
req->n_flows = remote->max_write;
req->state = TID_REQUEST_ACTIVE;
KDETH_RESET(ohdr->u.tid_rdma.w_req.kdeth0, KVER, 0x1);
KDETH_RESET(ohdr->u.tid_rdma.w_req.kdeth1, JKEY, remote->jkey);
ohdr->u.tid_rdma.w_req.reth.vaddr =
cpu_to_be64(wqe->rdma_wr.remote_addr + (wqe->length - *len));
ohdr->u.tid_rdma.w_req.reth.rkey =
cpu_to_be32(wqe->rdma_wr.rkey);
ohdr->u.tid_rdma.w_req.reth.length = cpu_to_be32(*len);
ohdr->u.tid_rdma.w_req.verbs_qp = cpu_to_be32(qp->remote_qpn);
*bth1 &= ~RVT_QPN_MASK;
*bth1 |= remote->qp;
qp->s_state = TID_OP(WRITE_REQ);
qp->s_flags |= HFI1_S_WAIT_TID_RESP;
*bth2 |= IB_BTH_REQ_ACK;
*len = 0;
rcu_read_unlock();
return sizeof(ohdr->u.tid_rdma.w_req) / sizeof(u32);
}

3
drivers/infiniband/hw/hfi1/tid_rdma.h
View File

@ -233,4 +233,7 @@ static inline void hfi1_setup_tid_rdma_wqe(struct rvt_qp *qp,
setup_tid_rdma_wqe(qp, wqe); setup_tid_rdma_wqe(qp, wqe);
} }
u32 hfi1_build_tid_rdma_write_req(struct rvt_qp *qp, struct rvt_swqe *wqe,
struct ib_other_headers *ohdr,
u32 *bth1, u32 *bth2, u32 *len);
#endif /* HFI1_TID_RDMA_H */ #endif /* HFI1_TID_RDMA_H */

5
include/rdma/ib_hdrs.h
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@ -123,6 +123,11 @@ union ib_ehdrs {
union { union {
struct tid_rdma_read_req r_req; struct tid_rdma_read_req r_req;
struct tid_rdma_read_resp r_rsp; struct tid_rdma_read_resp r_rsp;
struct tid_rdma_write_req w_req;
struct tid_rdma_write_resp w_rsp;
struct tid_rdma_write_data w_data;
struct tid_rdma_resync resync;
struct tid_rdma_ack ack;
} tid_rdma; } tid_rdma;
} __packed; } __packed;

56
include/rdma/tid_rdma_defs.h
View File

@ -27,16 +27,71 @@ struct tid_rdma_read_resp {
__be32 verbs_qp; __be32 verbs_qp;
}; };
struct tid_rdma_write_req {
__le32 kdeth0;
__le32 kdeth1;
struct ib_reth reth;
__be32 reserved[2];
__be32 verbs_qp;
};
struct tid_rdma_write_resp {
__le32 kdeth0;
__le32 kdeth1;
__be32 aeth;
__be32 reserved[3];
__be32 tid_flow_psn;
__be32 tid_flow_qp;
__be32 verbs_qp;
};
struct tid_rdma_write_data {
__le32 kdeth0;
__le32 kdeth1;
__be32 reserved[6];
__be32 verbs_qp;
};
struct tid_rdma_resync {
__le32 kdeth0;
__le32 kdeth1;
__be32 reserved[6];
__be32 verbs_qp;
};
struct tid_rdma_ack {
__le32 kdeth0;
__le32 kdeth1;
__be32 aeth;
__be32 reserved[2];
__be32 tid_flow_psn;
__be32 verbs_psn;
__be32 tid_flow_qp;
__be32 verbs_qp;
};
/* /*
* TID RDMA Opcodes * TID RDMA Opcodes
*/ */
#define IB_OPCODE_TID_RDMA 0xe0 #define IB_OPCODE_TID_RDMA 0xe0
enum { enum {
IB_OPCODE_WRITE_REQ = 0x0,
IB_OPCODE_WRITE_RESP = 0x1,
IB_OPCODE_WRITE_DATA = 0x2,
IB_OPCODE_WRITE_DATA_LAST = 0x3,
IB_OPCODE_READ_REQ = 0x4, IB_OPCODE_READ_REQ = 0x4,
IB_OPCODE_READ_RESP = 0x5, IB_OPCODE_READ_RESP = 0x5,
IB_OPCODE_RESYNC = 0x6,
IB_OPCODE_ACK = 0x7,
IB_OPCODE(TID_RDMA, WRITE_REQ),
IB_OPCODE(TID_RDMA, WRITE_RESP),
IB_OPCODE(TID_RDMA, WRITE_DATA),
IB_OPCODE(TID_RDMA, WRITE_DATA_LAST),
IB_OPCODE(TID_RDMA, READ_REQ), IB_OPCODE(TID_RDMA, READ_REQ),
IB_OPCODE(TID_RDMA, READ_RESP), IB_OPCODE(TID_RDMA, READ_RESP),
IB_OPCODE(TID_RDMA, RESYNC),
IB_OPCODE(TID_RDMA, ACK),
}; };
#define TID_OP(x) IB_OPCODE_TID_RDMA_##x #define TID_OP(x) IB_OPCODE_TID_RDMA_##x
@ -47,6 +102,7 @@ enum {
* low level drivers. Two of those are used but renamed * low level drivers. Two of those are used but renamed
* to be more descriptive. * to be more descriptive.
*/ */
#define IB_WR_TID_RDMA_WRITE IB_WR_RESERVED1
#define IB_WR_TID_RDMA_READ IB_WR_RESERVED2 #define IB_WR_TID_RDMA_READ IB_WR_RESERVED2
#endif /* TID_RDMA_DEFS_H */ #endif /* TID_RDMA_DEFS_H */