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iwlwifi: always check if got h/w access before write
Before we write to the device registers always check if iwl_grap_nic_access() was successful. On the way change return type of grab_nic_access() to bool, and add likely()/unlikely() statement. Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -189,7 +189,7 @@ static void iwl_tt_check_exit_ct_kill(unsigned long data)
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}
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iwl_read32(trans(priv), CSR_UCODE_DRV_GP1);
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spin_lock_irqsave(&trans(priv)->reg_lock, flags);
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if (!iwl_grab_nic_access(trans(priv)))
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if (likely(iwl_grab_nic_access(trans(priv))))
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iwl_release_nic_access(trans(priv));
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spin_unlock_irqrestore(&trans(priv)->reg_lock, flags);
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@ -327,7 +327,7 @@ static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
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/* Make sure device is powered up for SRAM reads */
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spin_lock_irqsave(&trans(priv)->reg_lock, reg_flags);
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if (iwl_grab_nic_access(trans(priv))) {
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if (unlikely(!iwl_grab_nic_access(trans(priv)))) {
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spin_unlock_irqrestore(&trans(priv)->reg_lock, reg_flags);
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return;
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}
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@ -118,16 +118,17 @@ int iwl_grab_nic_access_silent(struct iwl_trans *trans)
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return 0;
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}
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int iwl_grab_nic_access(struct iwl_trans *trans)
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bool iwl_grab_nic_access(struct iwl_trans *trans)
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{
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int ret = iwl_grab_nic_access_silent(trans);
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if (unlikely(ret)) {
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u32 val = iwl_read32(trans, CSR_GP_CNTRL);
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WARN_ONCE(1, "Timeout waiting for hardware access "
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"(CSR_GP_CNTRL 0x%08x)\n", val);
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return false;
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}
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return ret;
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return true;
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}
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void iwl_release_nic_access(struct iwl_trans *trans)
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@ -156,7 +157,7 @@ void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (!iwl_grab_nic_access(trans)) {
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if (likely(iwl_grab_nic_access(trans))) {
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iwl_write32(trans, reg, value);
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iwl_release_nic_access(trans);
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}
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@ -211,7 +212,7 @@ void iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (!iwl_grab_nic_access(trans)) {
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if (likely(iwl_grab_nic_access(trans))) {
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__iwl_write_prph(trans, addr, val);
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iwl_release_nic_access(trans);
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}
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@ -223,9 +224,11 @@ void iwl_set_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_grab_nic_access(trans);
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__iwl_write_prph(trans, reg, __iwl_read_prph(trans, reg) | mask);
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iwl_release_nic_access(trans);
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if (likely(iwl_grab_nic_access(trans))) {
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__iwl_write_prph(trans, reg,
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__iwl_read_prph(trans, reg) | mask);
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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@ -235,10 +238,11 @@ void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 reg,
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unsigned long flags;
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_grab_nic_access(trans);
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__iwl_write_prph(trans, reg,
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(__iwl_read_prph(trans, reg) & mask) | bits);
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iwl_release_nic_access(trans);
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if (likely(iwl_grab_nic_access(trans))) {
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__iwl_write_prph(trans, reg,
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(__iwl_read_prph(trans, reg) & mask) | bits);
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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@ -248,10 +252,11 @@ void iwl_clear_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
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u32 val;
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_grab_nic_access(trans);
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val = __iwl_read_prph(trans, reg);
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__iwl_write_prph(trans, reg, (val & ~mask));
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iwl_release_nic_access(trans);
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if (likely(iwl_grab_nic_access(trans))) {
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val = __iwl_read_prph(trans, reg);
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__iwl_write_prph(trans, reg, (val & ~mask));
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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@ -263,15 +268,13 @@ void _iwl_read_targ_mem_words(struct iwl_trans *trans, u32 addr,
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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iwl_grab_nic_access(trans);
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iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
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rmb();
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for (offs = 0; offs < words; offs++)
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vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
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iwl_release_nic_access(trans);
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if (likely(iwl_grab_nic_access(trans))) {
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iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
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rmb();
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for (offs = 0; offs < words; offs++)
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vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
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iwl_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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@ -292,7 +295,7 @@ int _iwl_write_targ_mem_words(struct iwl_trans *trans, u32 addr,
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (!iwl_grab_nic_access(trans)) {
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if (likely(iwl_grab_nic_access(trans))) {
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iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
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wmb();
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@ -61,7 +61,7 @@ int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
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int timeout);
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int iwl_grab_nic_access_silent(struct iwl_trans *trans);
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int iwl_grab_nic_access(struct iwl_trans *trans);
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bool iwl_grab_nic_access(struct iwl_trans *trans);
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void iwl_release_nic_access(struct iwl_trans *trans);
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u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg);
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@ -445,7 +445,7 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
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if (iwlagn_hw_valid_rtc_data_addr(base)) {
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spin_lock_irqsave(&trans(priv)->reg_lock, flags);
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ret = iwl_grab_nic_access_silent(trans(priv));
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if (ret == 0) {
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if (likely(ret == 0)) {
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iwl_write32(trans(priv), HBUS_TARG_MEM_RADDR, base);
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status = iwl_read32(trans(priv), HBUS_TARG_MEM_RDAT);
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iwl_release_nic_access(trans(priv));
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@ -745,7 +745,8 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
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/* Make sure device is powered up for SRAM reads */
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spin_lock_irqsave(&trans->reg_lock, reg_flags);
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iwl_grab_nic_access(trans);
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if (unlikely(!iwl_grab_nic_access(trans)))
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goto out_unlock;
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/* Set starting address; reads will auto-increment */
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iwl_write32(trans, HBUS_TARG_MEM_RADDR, ptr);
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@ -785,6 +786,7 @@ static int iwl_print_event_log(struct iwl_trans *trans, u32 start_idx,
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/* Allow device to power down */
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iwl_release_nic_access(trans);
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out_unlock:
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spin_unlock_irqrestore(&trans->reg_lock, reg_flags);
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return pos;
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}
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