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x86: cacheinfo: use L3 cache index disable feature only for CPUs that support it

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AMD family 0x11 CPU doesn't support the feature.

Some AMD family 0x10 CPUs do not support it or have an erratum, see
erratum #382 in "Revision Guide for AMD Family 10h Processors, 41322
Rev. 3.40 February 2009".

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
CC: Mark Langsdorf <mark.langsdorf@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <20090409130510.GG31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Andreas Herrmann 2009-04-09 15:05:10 +02:00 committed by Ingo Molnar
parent a0d22f485a
commit bda869c614
1 changed files with 8 additions and 0 deletions
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8
arch/x86/kernel/cpu/intel_cacheinfo.c
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@ -291,6 +291,14 @@ amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
{
if (index < 3)
return;
if (boot_cpu_data.x86 == 0x11)
return;
/* see erratum #382 */
if ((boot_cpu_data.x86 == 0x10) && (boot_cpu_data.x86_model < 0x8))
return;
this_leaf->can_disable = 1;
}