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drm/i915: rename INSTDONE to GEN2_INSTDONE

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We have a bunch of INSTDONE registers for different platforms and
purposes and it's not immediately clear which instance they are just by
looking at the register name. This one was added on GEN2, where it was
the only INSTDONE register, so mark it as such.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Imre Deak 2015-09-30 23:00:43 +03:00 committed by Daniel Vetter
parent f1d5434853
commit bd93a50e4d
2 changed files with 4 additions and 3 deletions
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4
drivers/gpu/drm/i915/i915_gpu_error.c
View File

@ -886,7 +886,7 @@ static void i915_record_ring_state(struct drm_device *dev,
ering->faddr = I915_READ(DMA_FADD_I8XX); ering->faddr = I915_READ(DMA_FADD_I8XX);
ering->ipeir = I915_READ(IPEIR); ering->ipeir = I915_READ(IPEIR);
ering->ipehr = I915_READ(IPEHR); ering->ipehr = I915_READ(IPEHR);
ering->instdone = I915_READ(INSTDONE); ering->instdone = I915_READ(GEN2_INSTDONE);
} }
ering->waiting = waitqueue_active(&ring->irq_queue); ering->waiting = waitqueue_active(&ring->irq_queue);
@ -1388,7 +1388,7 @@ void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone)
memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG); memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
if (IS_GEN2(dev) || IS_GEN3(dev)) if (IS_GEN2(dev) || IS_GEN3(dev))
instdone[0] = I915_READ(INSTDONE); instdone[0] = I915_READ(GEN2_INSTDONE);
else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) { else if (IS_GEN4(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE)); instdone[0] = I915_READ(RING_INSTDONE(RENDER_RING_BASE));
instdone[1] = I915_READ(INSTDONE1); instdone[1] = I915_READ(INSTDONE1);

3
drivers/gpu/drm/i915/i915_reg.h
View File

@ -1602,6 +1602,7 @@ enum skl_disp_power_wells {
/* /*
* On GEN4, only the render ring INSTDONE exists and has a different * On GEN4, only the render ring INSTDONE exists and has a different
* layout than the GEN7+ version. * layout than the GEN7+ version.
* The GEN2 counterpart of this register is GEN2_INSTDONE.
*/ */
#define RING_INSTDONE(base) ((base)+0x6c) #define RING_INSTDONE(base) ((base)+0x6c)
#define RING_INSTPS(base) ((base)+0x70) #define RING_INSTPS(base) ((base)+0x70)
@ -1619,7 +1620,7 @@ enum skl_disp_power_wells {
#define PWRCTX_EN (1<<0) #define PWRCTX_EN (1<<0)
#define IPEIR 0x02088 #define IPEIR 0x02088
#define IPEHR 0x0208c #define IPEHR 0x0208c
#define INSTDONE 0x02090 #define GEN2_INSTDONE 0x02090
#define NOPID 0x02094 #define NOPID 0x02094
#define HWSTAM 0x02098 #define HWSTAM 0x02098
#define DMA_FADD_I8XX 0x020d0 #define DMA_FADD_I8XX 0x020d0