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KVM: VMX: Add proper cache tracking for CR0
Move CR0 caching into the standard register caching mechanism in order to take advantage of the availability checks provided by regs_avail. This avoids multiple VMREADs in the (uncommon) case where kvm_read_cr0() is called multiple times in a single VM-Exit, and more importantly eliminates a kvm_x86_ops hook, saves a retpoline on SVM when reading CR0, and squashes the confusing naming discrepancy of "cache_reg" vs. "decache_cr0_guest_bits". No functional change intended. Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> Message-Id: <20200502043234.12481-8-sean.j.christopherson@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -167,6 +167,7 @@ enum kvm_reg {
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NR_VCPU_REGS,
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VCPU_EXREG_PDPTR = NR_VCPU_REGS,
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VCPU_EXREG_CR0,
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VCPU_EXREG_CR3,
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VCPU_EXREG_CR4,
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VCPU_EXREG_RFLAGS,
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@ -1092,7 +1093,6 @@ struct kvm_x86_ops {
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void (*set_segment)(struct kvm_vcpu *vcpu,
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struct kvm_segment *var, int seg);
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void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l);
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void (*decache_cr0_guest_bits)(struct kvm_vcpu *vcpu);
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void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
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int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
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void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
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@ -116,8 +116,9 @@ static inline u64 kvm_pdptr_read(struct kvm_vcpu *vcpu, int index)
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static inline ulong kvm_read_cr0_bits(struct kvm_vcpu *vcpu, ulong mask)
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{
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ulong tmask = mask & KVM_POSSIBLE_CR0_GUEST_BITS;
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if (tmask & vcpu->arch.cr0_guest_owned_bits)
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kvm_x86_ops.decache_cr0_guest_bits(vcpu);
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if ((tmask & vcpu->arch.cr0_guest_owned_bits) &&
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!kvm_register_is_available(vcpu, VCPU_EXREG_CR0))
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kvm_x86_ops.cache_reg(vcpu, VCPU_EXREG_CR0);
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return vcpu->arch.cr0 & mask;
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}
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@ -1521,10 +1521,6 @@ static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
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mark_dirty(svm->vmcb, VMCB_DT);
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}
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static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
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{
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}
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static void update_cr0_intercept(struct vcpu_svm *svm)
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{
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ulong gcr0 = svm->vcpu.arch.cr0;
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@ -4002,7 +3998,6 @@ static struct kvm_x86_ops svm_x86_ops __initdata = {
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.set_segment = svm_set_segment,
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.get_cpl = svm_get_cpl,
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.get_cs_db_l_bits = kvm_get_cs_db_l_bits,
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.decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
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.set_cr0 = svm_set_cr0,
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.set_cr4 = svm_set_cr4,
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.set_efer = svm_set_efer,
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@ -2219,6 +2219,12 @@ static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
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if (enable_ept)
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ept_save_pdptrs(vcpu);
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break;
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case VCPU_EXREG_CR0:
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guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
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vcpu->arch.cr0 &= ~guest_owned_bits;
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vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & guest_owned_bits;
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break;
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case VCPU_EXREG_CR3:
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if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
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vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
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@ -2922,14 +2928,6 @@ static void vmx_flush_tlb_guest(struct kvm_vcpu *vcpu)
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vpid_sync_context(to_vmx(vcpu)->vpid);
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}
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static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
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{
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ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
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vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
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vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
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}
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static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
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{
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struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
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@ -3019,6 +3017,7 @@ void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
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vmcs_writel(CR0_READ_SHADOW, cr0);
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vmcs_writel(GUEST_CR0, hw_cr0);
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vcpu->arch.cr0 = cr0;
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kvm_register_mark_available(vcpu, VCPU_EXREG_CR0);
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/* depends on vcpu->arch.cr0 to be set to a new value */
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vmx->emulation_required = emulation_required(vcpu);
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@ -7809,7 +7808,6 @@ static struct kvm_x86_ops vmx_x86_ops __initdata = {
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.set_segment = vmx_set_segment,
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.get_cpl = vmx_get_cpl,
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.get_cs_db_l_bits = vmx_get_cs_db_l_bits,
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.decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
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.set_cr0 = vmx_set_cr0,
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.set_cr4 = vmx_set_cr4,
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.set_efer = vmx_set_efer,
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@ -452,6 +452,7 @@ static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu)
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| (1 << VCPU_EXREG_RFLAGS)
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| (1 << VCPU_EXREG_PDPTR)
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| (1 << VCPU_EXREG_SEGMENTS)
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| (1 << VCPU_EXREG_CR0)
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| (1 << VCPU_EXREG_CR3)
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| (1 << VCPU_EXREG_CR4)
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| (1 << VCPU_EXREG_EXIT_INFO_1)
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