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ARM: dts: sun9i: a80-optimus: Enable GMAC

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The A80 Optimus has a Realtek RTL8211E ethernet PHY which uses RGMII to
talk to the MAC. The PHY is powered by 2 regulators: cldo1 for the PHY's
core logic and gpio1-ldo for I/O. The latter also powers the SoC side
pins. As there is no binding to model a second regulator supply for the
PHY, it is omitted. It is however properly modeled for the PIO.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
This commit is contained in:
Chen-Yu Tsai 2019-02-06 11:32:38 +08:00 committed by Maxime Ripard
parent 72acaa1343
commit bc9bd03a44
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GPG Key ID: E3EF0D6F671851C5
1 changed files with 21 additions and 0 deletions
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21
arch/arm/boot/dts/sun9i-a80-optimus.dts
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@ -120,6 +120,19 @@
status = "okay";
};
&gmac {
pinctrl-names = "default";
pinctrl-0 = <&gmac_rgmii_pins>;
phy = <&phy1>;
phy-mode = "rgmii";
phy-supply = <&reg_cldo1>;
status = "okay";
phy1: ethernet-phy@1 {
reg = <1>;
};
};
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@ -391,6 +404,14 @@
*/
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
/*
* The PHY requires 20ms after all voltages
* are applied until core logic is ready and
* 30ms after the reset pin is de-asserted.
* Set a 100ms delay to account for PMIC
* ramp time and board traces.
*/
regulator-enable-ramp-delay = <100000>;
regulator-name = "vcc-gmac-phy";
};