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parisc: add support for TOC (transfer of control)
Almost all PA-RISC machines have either a button that is labeled with 'TOC' or a BMC function to trigger a TOC. TOC is a non-maskable interrupt that is sent to the processor. This can be used for diagnostic purposes like obtaining a stack trace/register dump or to enter KDB/KGDB. As an example, on my c8000, TOC can be used with: CONFIG_KGDB=y CONFIG_KGDB_KDB=y and the 'kgdboc=ttyS0,115200' appended to the command line. Press ^[( on serial console, which will enter the BMC command line, and enter 'TOC s': root@(none):/# ( cli>TOC s Sending TOC/INIT. <Cpu3> 2800035d03e00000 0000000040c21ac8 CC_ERR_CHECK_TOC <Cpu0> 2800035d00e00000 0000000040c21ad0 CC_ERR_CHECK_TOC <Cpu2> 2800035d02e00000 0000000040c21ac8 CC_ERR_CHECK_TOC <Cpu1> 2800035d01e00000 0000000040c21ad0 CC_ERR_CHECK_TOC <Cpu3> 37000f7303e00000 2000000000000000 CC_ERR_CPU_CHECK_SUMMARY <Cpu0> 37000f7300e00000 2000000000000000 CC_ERR_CPU_CHECK_SUMMARY <Cpu2> 37000f7302e00000 2000000000000000 CC_ERR_CPU_CHECK_SUMMARY <Cpu1> 37000f7301e00000 2000000000000000 CC_ERR_CPU_CHECK_SUMMARY <Cpu3> 4300100803e00000 c0000000001d26cc CC_MC_BR_TO_OS_TOC <Cpu0> 4300100800e00000 c0000000001d26cc CC_MC_BR_TO_OS_TOC <Cpu2> 4300100802e00000 c0000000001d26cc CC_MC_BR_TO_OS_TOC <Cpu1> 4300100801e00000 c0000000001d26cc CC_MC_BR_TO_OS_TOC Entering kdb (current=0x00000000411cef80, pid 0) on processor 0 due to NonMaskable Interrupt @ 0x40c21ad0 [0]kdb> Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
Sven Schnelle
Helge Deller
parent
ecac70366d
commit
bc294838cc
@ -291,6 +291,20 @@ config SMP
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If you don't know what to do here, say N.
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config TOC
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bool "Support TOC switch"
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default y if 64BIT || !SMP
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help
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Most PA-RISC machines have either a switch at the back of the machine
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or a command in BMC to trigger a TOC interrupt. If you say Y here a
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handler will be installed which will either show a backtrace on all
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CPUs, or enter a possible configured debugger like kgdb/kdb.
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Note that with this option enabled, the kernel will use an additional 16KB
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per possible CPU as a special stack for the TOC handler.
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If you don't want to debug the Kernel, say N.
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config PARISC_CPU_TOPOLOGY
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bool "Support cpu topology definition"
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depends on SMP
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@ -295,6 +295,10 @@ extern int _parisc_requires_coherency;
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extern int running_on_qemu;
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extern void toc_handler(void);
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extern unsigned int toc_handler_size;
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extern unsigned int toc_handler_csum;
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_PARISC_PROCESSOR_H */
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@ -398,8 +398,10 @@ struct zeropage {
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/* int (*vec_rendz)(void); */
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unsigned int vec_rendz;
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int vec_pow_fail_flen;
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int vec_pad[10];
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int vec_pad0[3];
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unsigned int vec_toc_hi;
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int vec_pad1[6];
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/* [0x040] reserved processor dependent */
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int pad0[112];
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@ -39,3 +39,4 @@ obj-$(CONFIG_KGDB) += kgdb.o
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obj-$(CONFIG_KPROBES) += kprobes.o
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obj-$(CONFIG_KEXEC_CORE) += kexec.o relocate_kernel.o
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obj-$(CONFIG_KEXEC_FILE) += kexec_file.o
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obj-$(CONFIG_TOC) += toc.o toc_asm.o
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111
arch/parisc/kernel/toc.c
Normal file
111
arch/parisc/kernel/toc.c
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@ -0,0 +1,111 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/kernel.h>
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#include <linux/kgdb.h>
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#include <linux/printk.h>
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#include <linux/sched/debug.h>
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#include <linux/delay.h>
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#include <linux/reboot.h>
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#include <asm/pdc.h>
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#include <asm/pdc_chassis.h>
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unsigned int __aligned(16) toc_lock = 1;
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static void toc20_to_pt_regs(struct pt_regs *regs, struct pdc_toc_pim_20 *toc)
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{
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int i;
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regs->gr[0] = (unsigned long)toc->cr[22];
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for (i = 1; i < 32; i++)
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regs->gr[i] = (unsigned long)toc->gr[i];
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for (i = 0; i < 8; i++)
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regs->sr[i] = (unsigned long)toc->sr[i];
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regs->iasq[0] = (unsigned long)toc->cr[17];
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regs->iasq[1] = (unsigned long)toc->iasq_back;
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regs->iaoq[0] = (unsigned long)toc->cr[18];
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regs->iaoq[1] = (unsigned long)toc->iaoq_back;
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regs->sar = (unsigned long)toc->cr[11];
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regs->iir = (unsigned long)toc->cr[19];
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regs->isr = (unsigned long)toc->cr[20];
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regs->ior = (unsigned long)toc->cr[21];
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}
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static void toc11_to_pt_regs(struct pt_regs *regs, struct pdc_toc_pim_11 *toc)
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{
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int i;
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regs->gr[0] = toc->cr[22];
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for (i = 1; i < 32; i++)
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regs->gr[i] = toc->gr[i];
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for (i = 0; i < 8; i++)
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regs->sr[i] = toc->sr[i];
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regs->iasq[0] = toc->cr[17];
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regs->iasq[1] = toc->iasq_back;
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regs->iaoq[0] = toc->cr[18];
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regs->iaoq[1] = toc->iaoq_back;
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regs->sar = toc->cr[11];
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regs->iir = toc->cr[19];
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regs->isr = toc->cr[20];
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regs->ior = toc->cr[21];
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}
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void notrace __noreturn __cold toc_intr(struct pt_regs *regs)
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{
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struct pdc_toc_pim_20 pim_data20;
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struct pdc_toc_pim_11 pim_data11;
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nmi_enter();
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if (boot_cpu_data.cpu_type >= pcxu) {
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if (pdc_pim_toc20(&pim_data20))
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panic("Failed to get PIM data");
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toc20_to_pt_regs(regs, &pim_data20);
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} else {
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if (pdc_pim_toc11(&pim_data11))
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panic("Failed to get PIM data");
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toc11_to_pt_regs(regs, &pim_data11);
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}
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#ifdef CONFIG_KGDB
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if (atomic_read(&kgdb_active) != -1)
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kgdb_nmicallback(raw_smp_processor_id(), regs);
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kgdb_handle_exception(9, SIGTRAP, 0, regs);
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#endif
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show_regs(regs);
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/* give other CPUs time to show their backtrace */
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mdelay(2000);
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machine_restart("TOC");
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/* should never reach this */
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panic("TOC");
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}
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static __init int setup_toc(void)
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{
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unsigned int csum = 0;
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unsigned long toc_code = (unsigned long)dereference_function_descriptor(toc_handler);
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int i;
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PAGE0->vec_toc = __pa(toc_code) & 0xffffffff;
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#ifdef CONFIG_64BIT
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PAGE0->vec_toc_hi = __pa(toc_code) >> 32;
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#endif
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PAGE0->vec_toclen = toc_handler_size;
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for (i = 0; i < toc_handler_size/4; i++)
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csum += ((u32 *)toc_code)[i];
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toc_handler_csum = -csum;
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pr_info("TOC handler registered\n");
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return 0;
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}
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early_initcall(setup_toc);
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88
arch/parisc/kernel/toc_asm.S
Normal file
88
arch/parisc/kernel/toc_asm.S
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@ -0,0 +1,88 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* TOC (Transfer of Control) handler. */
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.level 1.1
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#include <asm/assembly.h>
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#include <asm/psw.h>
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#include <linux/threads.h>
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#include <linux/linkage.h>
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.text
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.import toc_intr,code
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.import toc_lock,data
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.align 16
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ENTRY_CFI(toc_handler)
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/*
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* synchronize CPUs and obtain offset
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* for stack setup.
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*/
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load32 PA(toc_lock),%r1
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0: ldcw,co 0(%r1),%r2
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cmpib,= 0,%r2,0b
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nop
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addi 1,%r2,%r4
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stw %r4,0(%r1)
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addi -1,%r2,%r4
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load32 PA(toc_stack),%sp
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/*
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* deposit CPU number into stack address,
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* so every CPU will have its own stack.
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*/
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SHLREG %r4,14,%r4
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add %r4,%sp,%sp
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/*
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* setup pt_regs on stack and save the
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* floating point registers. PIM_TOC doesn't
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* save fp registers, so we're doing it here.
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*/
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copy %sp,%arg0
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ldo PT_SZ_ALGN(%sp), %sp
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/* clear pt_regs */
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copy %arg0,%r1
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0: cmpb,<<,n %r1,%sp,0b
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stw,ma %r0,4(%r1)
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ldo PT_FR0(%arg0),%r25
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save_fp %r25
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/* go virtual */
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load32 PA(swapper_pg_dir),%r4
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mtctl %r4,%cr24
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mtctl %r4,%cr25
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/* Clear sr4-sr7 */
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mtsp %r0, %sr4
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mtsp %r0, %sr5
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mtsp %r0, %sr6
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mtsp %r0, %sr7
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tovirt_r1 %sp
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tovirt_r1 %arg0
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virt_map
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loadgp
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#ifdef CONFIG_64BIT
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ldo -16(%sp),%r29
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#endif
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load32 toc_intr,%r1
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be 0(%sr7,%r1)
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nop
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ENDPROC_CFI(toc_handler)
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/*
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* keep this checksum here, as it is part of the toc_handler
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* spanned by toc_handler_size (all words in toc_handler are
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* added in PDC and the sum must equal to zero.
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*/
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SYM_DATA(toc_handler_csum, .long 0)
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SYM_DATA(toc_handler_size, .long . - toc_handler)
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__PAGE_ALIGNED_BSS
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.align 64
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SYM_DATA(toc_stack, .block 16384*NR_CPUS)
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