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drm/i915: Inline I915_INTERRUPT_ENABLE_FIX
Since there is only one remaining user of I915_INTERRUPT_ENABLE_FIX, expand it at the callsite. Quoting Jesse Barnes: "I'd really like to get rid of these defines at the top of i915_irq.c. Some are unused and the others just make you check for the right bits everytime your read the code." Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> [danvet: Add bikeshed suggested by Jesse.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -39,24 +39,6 @@
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#define MAX_NOPID ((u32)~0)
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#define MAX_NOPID ((u32)~0)
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/**
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* Interrupts that are always left unmasked.
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*
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* Since pipe events are edge-triggered from the PIPESTAT register to IIR,
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* we leave them always unmasked in IMR and then control enabling them through
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* PIPESTAT alone.
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*/
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#define I915_INTERRUPT_ENABLE_FIX \
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(I915_ASLE_INTERRUPT | \
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
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I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
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/** Interrupts that we mask and unmask at runtime. */
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#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
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#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
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#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
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PIPE_VBLANK_INTERRUPT_STATUS)
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PIPE_VBLANK_INTERRUPT_STATUS)
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@ -2581,13 +2563,24 @@ static void i965_irq_preinstall(struct drm_device * dev)
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static int i965_irq_postinstall(struct drm_device *dev)
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static int i965_irq_postinstall(struct drm_device *dev)
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{
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
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u32 enable_mask;
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u32 error_mask;
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u32 error_mask;
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
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/* Unmask the interrupts that we always want on. */
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/* Unmask the interrupts that we always want on. */
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dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
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dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
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I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
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I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
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I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
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I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
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I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
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enable_mask = ~dev_priv->irq_mask;
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enable_mask |= I915_USER_INTERRUPT;
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if (IS_G4X(dev))
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enable_mask |= I915_BSD_USER_INTERRUPT;
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dev_priv->pipestat[0] = 0;
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dev_priv->pipestat[0] = 0;
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dev_priv->pipestat[1] = 0;
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dev_priv->pipestat[1] = 0;
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