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x86: use cpuid vector 0xb when available for detecting cpu topology
cpuid leaf 0xb provides extended topology enumeration. This interface provides the 32-bit x2APIC id of the logical processor and it also provides a new mechanism to detect SMT and core siblings (which provides increased addressability). Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -7,6 +7,8 @@
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#include <asm/pat.h>
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#include <asm/processor.h>
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#include <mach_apic.h>
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struct cpuid_bit {
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u16 feature;
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u8 reg;
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@ -48,6 +50,90 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
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}
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}
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/* leaf 0xb SMT level */
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#define SMT_LEVEL 0
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/* leaf 0xb sub-leaf types */
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#define INVALID_TYPE 0
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#define SMT_TYPE 1
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#define CORE_TYPE 2
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#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
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#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
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#define LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff)
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/*
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* Check for extended topology enumeration cpuid leaf 0xb and if it
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* exists, use it for populating initial_apicid and cpu topology
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* detection.
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*/
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void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
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{
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unsigned int eax, ebx, ecx, edx, sub_index;
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unsigned int ht_mask_width, core_plus_mask_width;
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unsigned int core_select_mask, core_level_siblings;
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if (c->cpuid_level < 0xb)
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return;
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cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
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/*
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* check if the cpuid leaf 0xb is actually implemented.
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*/
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if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE))
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return;
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set_cpu_cap(c, X86_FEATURE_XTOPOLOGY);
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/*
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* initial apic id, which also represents 32-bit extended x2apic id.
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*/
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c->initial_apicid = edx;
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/*
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* Populate HT related information from sub-leaf level 0.
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*/
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core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx);
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core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
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sub_index = 1;
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do {
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cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
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/*
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* Check for the Core type in the implemented sub leaves.
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*/
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if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
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core_level_siblings = LEVEL_MAX_SIBLINGS(ebx);
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core_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
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break;
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}
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sub_index++;
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} while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
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core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width;
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#ifdef CONFIG_X86_32
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c->cpu_core_id = phys_pkg_id(c->initial_apicid, ht_mask_width)
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& core_select_mask;
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c->phys_proc_id = phys_pkg_id(c->initial_apicid, core_plus_mask_width);
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#else
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c->cpu_core_id = phys_pkg_id(ht_mask_width) & core_select_mask;
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c->phys_proc_id = phys_pkg_id(core_plus_mask_width);
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#endif
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c->x86_max_cores = (core_level_siblings / smp_num_siblings);
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printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
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c->phys_proc_id);
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if (c->x86_max_cores > 1)
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printk(KERN_INFO "CPU: Processor Core ID: %d\n",
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c->cpu_core_id);
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return;
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}
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#ifdef CONFIG_X86_PAT
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void __cpuinit validate_pat_support(struct cpuinfo_x86 *c)
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{
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@ -128,6 +128,9 @@ void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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u32 eax, ebx, ecx, edx;
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int index_msb, core_bits;
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if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
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return;
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cpuid(1, &eax, &ebx, &ecx, &edx);
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@ -176,9 +176,16 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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if (p)
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strcpy(c->x86_model_id, p);
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c->x86_max_cores = num_cpu_cores(c);
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detect_extended_topology(c);
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if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
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/*
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* let's use the legacy cpuid vector 0x1 and 0x4 for topology
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* detection.
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*/
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c->x86_max_cores = num_cpu_cores(c);
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detect_ht(c);
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}
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/* Work around errata */
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Intel_errata_workarounds(c);
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@ -80,6 +80,9 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
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if (c->x86 == 6)
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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detect_extended_topology(c);
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if (!cpu_has(c, X86_FEATURE_XTOPOLOGY))
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c->x86_max_cores = intel_num_cpu_cores(c);
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srat_detect_node();
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@ -81,6 +81,7 @@
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#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
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#define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */
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#define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_XTOPOLOGY (3*32+21) /* cpu topology enum extensions */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
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@ -161,6 +161,7 @@ extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
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extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
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extern unsigned short num_cache_leaves;
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extern void detect_extended_topology(struct cpuinfo_x86 *c);
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#if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
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extern void detect_ht(struct cpuinfo_x86 *c);
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#else
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