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tilegx pci: support I/O to arbitrarily-cached pages
The tilegx PCI root complex support (currently only in linux-next) is limited to pages that are homed on cached in the default manner, i.e. "hash-for-home". This change supports delivery of I/O data to pages that are cached in other ways (locally on a particular core, uncached, user-managed incoherent, etc.). A large part of the change is supporting flushing pages from cache on particular homes so that we can transition the data that we are delivering to or from the device appropriately. The new homecache_finv* routines handle this. Some changes to page_table_range_init() were also required to make the fixmap code work correctly on tilegx; it hadn't been used there before. We also remove some stub mark_caches_evicted_*() routines that were just no-ops anyway. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
This commit is contained in:
Chris Metcalf
parent
3e219b9153
commit
bbaa22c3a0
@ -27,11 +27,17 @@
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#define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
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/*
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* TILE-Gx is fully coherent so we don't need to define ARCH_DMA_MINALIGN.
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* TILEPro I/O is not always coherent (networking typically uses coherent
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* I/O, but PCI traffic does not) and setting ARCH_DMA_MINALIGN to the
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* L2 cacheline size helps ensure that kernel heap allocations are aligned.
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* TILE-Gx I/O is always coherent when used on hash-for-home pages.
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*
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* However, it's possible at runtime to request not to use hash-for-home
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* for the kernel heap, in which case the kernel will use flush-and-inval
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* to manage coherence. As a result, we use L2_CACHE_BYTES for the
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* DMA minimum alignment to avoid false sharing in the kernel heap.
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*/
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#ifndef __tilegx__
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#define ARCH_DMA_MINALIGN L2_CACHE_BYTES
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#endif
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/* use the cache line size for the L2, which is where it counts */
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#define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT
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@ -45,14 +45,22 @@
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*
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* TLB entries of such buffers will not be flushed across
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* task switches.
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*
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* We don't bother with a FIX_HOLE since above the fixmaps
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* is unmapped memory in any case.
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*/
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enum fixed_addresses {
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#ifdef __tilegx__
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/*
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* TILEPro has unmapped memory above so the hole isn't needed,
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* and in any case the hole pushes us over a single 16MB pmd.
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*/
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FIX_HOLE,
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#endif
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#ifdef CONFIG_HIGHMEM
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FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
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FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
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#endif
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#ifdef __tilegx__ /* see homecache.c */
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FIX_HOMECACHE_BEGIN,
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FIX_HOMECACHE_END = FIX_HOMECACHE_BEGIN+(NR_CPUS)-1,
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#endif
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__end_of_permanent_fixed_addresses,
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@ -79,10 +79,17 @@ extern void homecache_change_page_home(struct page *, int order, int home);
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/*
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* Flush a page out of whatever cache(s) it is in.
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* This is more than just finv, since it properly handles waiting
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* for the data to reach memory on tilepro, but it can be quite
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* heavyweight, particularly on hash-for-home memory.
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* for the data to reach memory, but it can be quite
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* heavyweight, particularly on incoherent or immutable memory.
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*/
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extern void homecache_flush_cache(struct page *, int order);
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extern void homecache_finv_page(struct page *);
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/*
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* Flush a page out of the specified home cache.
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* Note that the specified home need not be the actual home of the page,
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* as for example might be the case when coordinating with I/O devices.
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*/
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extern void homecache_finv_map_page(struct page *, int home);
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/*
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* Allocate a page with the given GFP flags, home, and optionally
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@ -104,10 +111,10 @@ extern struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
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* routines use homecache_change_page_home() to reset the home
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* back to the default before returning the page to the allocator.
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*/
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void __homecache_free_pages(struct page *, unsigned int order);
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void homecache_free_pages(unsigned long addr, unsigned int order);
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#define homecache_free_page(page) \
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homecache_free_pages((page), 0)
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#define __homecache_free_page(page) __homecache_free_pages((page), 0)
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#define homecache_free_page(page) homecache_free_pages((page), 0)
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/*
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@ -174,7 +174,9 @@ static inline __attribute_const__ int get_order(unsigned long size)
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#define MEM_LOW_END (HALF_VA_SPACE - 1) /* low half */
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#define MEM_HIGH_START (-HALF_VA_SPACE) /* high half */
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#define PAGE_OFFSET MEM_HIGH_START
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#define _VMALLOC_START _AC(0xfffffff500000000, UL) /* 4 GB */
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#define FIXADDR_BASE _AC(0xfffffff400000000, UL) /* 4 GB */
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#define FIXADDR_TOP _AC(0xfffffff500000000, UL) /* 4 GB */
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#define _VMALLOC_START FIXADDR_TOP
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#define HUGE_VMAP_BASE _AC(0xfffffff600000000, UL) /* 4 GB */
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#define MEM_SV_START _AC(0xfffffff700000000, UL) /* 256 MB */
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#define MEM_SV_INTRPT MEM_SV_START
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@ -185,9 +187,6 @@ static inline __attribute_const__ int get_order(unsigned long size)
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/* Highest DTLB address we will use */
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#define KERNEL_HIGH_VADDR MEM_SV_START
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/* Since we don't currently provide any fixmaps, we use an impossible VA. */
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#define FIXADDR_TOP MEM_HV_START
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#else /* !__tilegx__ */
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/*
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@ -22,9 +22,15 @@
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/* Generic DMA mapping functions: */
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/*
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* Allocate what Linux calls "coherent" memory, which for us just
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* means uncached.
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* Allocate what Linux calls "coherent" memory. On TILEPro this is
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* uncached memory; on TILE-Gx it is hash-for-home memory.
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*/
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#ifdef __tilepro__
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#define PAGE_HOME_DMA PAGE_HOME_UNCACHED
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#else
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#define PAGE_HOME_DMA PAGE_HOME_HASH
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#endif
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void *dma_alloc_coherent(struct device *dev,
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size_t size,
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dma_addr_t *dma_handle,
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@ -48,13 +54,13 @@ void *dma_alloc_coherent(struct device *dev,
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if (dma_mask <= DMA_BIT_MASK(32))
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node = 0;
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pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_UNCACHED);
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pg = homecache_alloc_pages_node(node, gfp, order, PAGE_HOME_DMA);
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if (pg == NULL)
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return NULL;
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addr = page_to_phys(pg);
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if (addr + size > dma_mask) {
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homecache_free_pages(addr, order);
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__homecache_free_pages(pg, order);
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return NULL;
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}
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@ -87,22 +93,110 @@ EXPORT_SYMBOL(dma_free_coherent);
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* can count on nothing having been touched.
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*/
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/* Flush a PA range from cache page by page. */
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static void __dma_map_pa_range(dma_addr_t dma_addr, size_t size)
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/* Set up a single page for DMA access. */
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static void __dma_prep_page(struct page *page, unsigned long offset,
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size_t size, enum dma_data_direction direction)
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{
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/*
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* Flush the page from cache if necessary.
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* On tilegx, data is delivered to hash-for-home L3; on tilepro,
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* data is delivered direct to memory.
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*
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* NOTE: If we were just doing DMA_TO_DEVICE we could optimize
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* this to be a "flush" not a "finv" and keep some of the
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* state in cache across the DMA operation, but it doesn't seem
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* worth creating the necessary flush_buffer_xxx() infrastructure.
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*/
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int home = page_home(page);
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switch (home) {
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case PAGE_HOME_HASH:
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#ifdef __tilegx__
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return;
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#endif
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break;
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case PAGE_HOME_UNCACHED:
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#ifdef __tilepro__
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return;
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#endif
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break;
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case PAGE_HOME_IMMUTABLE:
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/* Should be going to the device only. */
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BUG_ON(direction == DMA_FROM_DEVICE ||
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direction == DMA_BIDIRECTIONAL);
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return;
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case PAGE_HOME_INCOHERENT:
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/* Incoherent anyway, so no need to work hard here. */
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return;
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default:
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BUG_ON(home < 0 || home >= NR_CPUS);
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break;
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}
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homecache_finv_page(page);
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#ifdef DEBUG_ALIGNMENT
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/* Warn if the region isn't cacheline aligned. */
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if (offset & (L2_CACHE_BYTES - 1) || (size & (L2_CACHE_BYTES - 1)))
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pr_warn("Unaligned DMA to non-hfh memory: PA %#llx/%#lx\n",
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PFN_PHYS(page_to_pfn(page)) + offset, size);
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#endif
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}
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/* Make the page ready to be read by the core. */
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static void __dma_complete_page(struct page *page, unsigned long offset,
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size_t size, enum dma_data_direction direction)
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{
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#ifdef __tilegx__
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switch (page_home(page)) {
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case PAGE_HOME_HASH:
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/* I/O device delivered data the way the cpu wanted it. */
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break;
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case PAGE_HOME_INCOHERENT:
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/* Incoherent anyway, so no need to work hard here. */
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break;
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case PAGE_HOME_IMMUTABLE:
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/* Extra read-only copies are not a problem. */
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break;
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default:
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/* Flush the bogus hash-for-home I/O entries to memory. */
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homecache_finv_map_page(page, PAGE_HOME_HASH);
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break;
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}
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#endif
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}
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static void __dma_prep_pa_range(dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
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size_t bytesleft = PAGE_SIZE - (dma_addr & (PAGE_SIZE - 1));
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unsigned long offset = dma_addr & (PAGE_SIZE - 1);
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size_t bytes = min(size, (size_t)(PAGE_SIZE - offset));
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while ((ssize_t)size > 0) {
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/* Flush the page. */
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homecache_flush_cache(page++, 0);
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/* Figure out if we need to continue on the next page. */
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size -= bytesleft;
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bytesleft = PAGE_SIZE;
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while (size != 0) {
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__dma_prep_page(page, offset, bytes, direction);
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size -= bytes;
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++page;
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offset = 0;
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bytes = min((size_t)PAGE_SIZE, size);
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}
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}
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static void __dma_complete_pa_range(dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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struct page *page = pfn_to_page(PFN_DOWN(dma_addr));
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unsigned long offset = dma_addr & (PAGE_SIZE - 1);
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size_t bytes = min(size, (size_t)(PAGE_SIZE - offset));
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while (size != 0) {
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__dma_complete_page(page, offset, bytes, direction);
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size -= bytes;
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++page;
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offset = 0;
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bytes = min((size_t)PAGE_SIZE, size);
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}
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}
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/*
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* dma_map_single can be passed any memory address, and there appear
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* to be no alignment constraints.
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@ -118,7 +212,7 @@ dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(size == 0);
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__dma_map_pa_range(dma_addr, size);
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__dma_prep_pa_range(dma_addr, size, direction);
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return dma_addr;
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}
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@ -128,6 +222,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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__dma_complete_pa_range(dma_addr, size, direction);
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}
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EXPORT_SYMBOL(dma_unmap_single);
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@ -143,17 +238,25 @@ int dma_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
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for_each_sg(sglist, sg, nents, i) {
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sg->dma_address = sg_phys(sg);
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__dma_map_pa_range(sg->dma_address, sg->length);
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__dma_prep_pa_range(sg->dma_address, sg->length, direction);
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}
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return nents;
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}
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EXPORT_SYMBOL(dma_map_sg);
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void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
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void dma_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
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enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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for_each_sg(sglist, sg, nents, i) {
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sg->dma_address = sg_phys(sg);
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__dma_complete_pa_range(sg->dma_address, sg->length,
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direction);
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}
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}
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EXPORT_SYMBOL(dma_unmap_sg);
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@ -164,8 +267,7 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page,
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BUG_ON(!valid_dma_direction(direction));
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BUG_ON(offset + size > PAGE_SIZE);
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homecache_flush_cache(page, 0);
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__dma_prep_page(page, offset, size, direction);
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return page_to_pa(page) + offset;
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}
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EXPORT_SYMBOL(dma_map_page);
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@ -174,6 +276,8 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
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enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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__dma_complete_page(pfn_to_page(PFN_DOWN(dma_address)),
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dma_address & PAGE_OFFSET, size, direction);
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}
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EXPORT_SYMBOL(dma_unmap_page);
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@ -181,33 +285,33 @@ void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction)
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{
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BUG_ON(!valid_dma_direction(direction));
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__dma_complete_pa_range(dma_handle, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_for_cpu);
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void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction direction)
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{
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unsigned long start = PFN_DOWN(dma_handle);
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unsigned long end = PFN_DOWN(dma_handle + size - 1);
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unsigned long i;
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BUG_ON(!valid_dma_direction(direction));
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for (i = start; i <= end; ++i)
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homecache_flush_cache(pfn_to_page(i), 0);
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__dma_prep_pa_range(dma_handle, size, direction);
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}
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EXPORT_SYMBOL(dma_sync_single_for_device);
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void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nelems,
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enum dma_data_direction direction)
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void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction)
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{
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struct scatterlist *sg;
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int i;
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BUG_ON(!valid_dma_direction(direction));
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WARN_ON(nelems == 0 || sg[0].length == 0);
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WARN_ON(nelems == 0 || sglist->length == 0);
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for_each_sg(sglist, sg, nelems, i) {
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dma_sync_single_for_cpu(dev, sg->dma_address,
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sg_dma_len(sg), direction);
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}
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}
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EXPORT_SYMBOL(dma_sync_sg_for_cpu);
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/*
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* Flush and invalidate cache for scatterlist.
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*/
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void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sglist,
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int nelems, enum dma_data_direction direction)
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{
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@ -242,8 +346,8 @@ void dma_sync_single_range_for_device(struct device *dev,
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EXPORT_SYMBOL(dma_sync_single_range_for_device);
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/*
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* dma_alloc_noncoherent() returns non-cacheable memory, so there's no
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* need to do any flushing here.
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* dma_alloc_noncoherent() is #defined to return coherent memory,
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* so there's no need to do any flushing here.
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*/
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void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
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enum dma_data_direction direction)
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@ -64,10 +64,6 @@ early_param("noallocl2", set_noallocl2);
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#endif
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/* Provide no-op versions of these routines to keep flush_remote() cleaner. */
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#define mark_caches_evicted_start() 0
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#define mark_caches_evicted_finish(mask, timestamp) do {} while (0)
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/*
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* Update the irq_stat for cpus that we are going to interrupt
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@ -107,7 +103,6 @@ static void hv_flush_update(const struct cpumask *cache_cpumask,
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* there's never any good reason for hv_flush_remote() to fail.
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* - Accepts a 32-bit PFN rather than a 64-bit PA, which generally
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* is the type that Linux wants to pass around anyway.
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* - Centralizes the mark_caches_evicted() handling.
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* - Canonicalizes that lengths of zero make cpumasks NULL.
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* - Handles deferring TLB flushes for dataplane tiles.
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* - Tracks remote interrupts in the per-cpu irq_cpustat_t.
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@ -126,7 +121,6 @@ void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
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HV_Remote_ASID *asids, int asidcount)
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{
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int rc;
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int timestamp = 0; /* happy compiler */
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struct cpumask cache_cpumask_copy, tlb_cpumask_copy;
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struct cpumask *cache_cpumask, *tlb_cpumask;
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HV_PhysAddr cache_pa;
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@ -157,15 +151,11 @@ void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
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hv_flush_update(cache_cpumask, tlb_cpumask, tlb_va, tlb_length,
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||||
asids, asidcount);
|
||||
cache_pa = (HV_PhysAddr)cache_pfn << PAGE_SHIFT;
|
||||
if (cache_control & HV_FLUSH_EVICT_L2)
|
||||
timestamp = mark_caches_evicted_start();
|
||||
rc = hv_flush_remote(cache_pa, cache_control,
|
||||
cpumask_bits(cache_cpumask),
|
||||
tlb_va, tlb_length, tlb_pgsize,
|
||||
cpumask_bits(tlb_cpumask),
|
||||
asids, asidcount);
|
||||
if (cache_control & HV_FLUSH_EVICT_L2)
|
||||
mark_caches_evicted_finish(cache_cpumask, timestamp);
|
||||
if (rc == 0)
|
||||
return;
|
||||
cpumask_scnprintf(cache_buf, sizeof(cache_buf), &cache_cpumask_copy);
|
||||
@ -180,86 +170,87 @@ void flush_remote(unsigned long cache_pfn, unsigned long cache_control,
|
||||
panic("Unsafe to continue.");
|
||||
}
|
||||
|
||||
void flush_remote_page(struct page *page, int order)
|
||||
static void homecache_finv_page_va(void* va, int home)
|
||||
{
|
||||
int i, pages = (1 << order);
|
||||
for (i = 0; i < pages; ++i, ++page) {
|
||||
void *p = kmap_atomic(page);
|
||||
int hfh = 0;
|
||||
int home = page_home(page);
|
||||
#if CHIP_HAS_CBOX_HOME_MAP()
|
||||
if (home == PAGE_HOME_HASH)
|
||||
hfh = 1;
|
||||
else
|
||||
#endif
|
||||
if (home == smp_processor_id()) {
|
||||
finv_buffer_local(va, PAGE_SIZE);
|
||||
} else if (home == PAGE_HOME_HASH) {
|
||||
finv_buffer_remote(va, PAGE_SIZE, 1);
|
||||
} else {
|
||||
BUG_ON(home < 0 || home >= NR_CPUS);
|
||||
finv_buffer_remote(p, PAGE_SIZE, hfh);
|
||||
kunmap_atomic(p);
|
||||
finv_buffer_remote(va, PAGE_SIZE, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void homecache_finv_map_page(struct page *page, int home)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long va;
|
||||
pte_t *ptep;
|
||||
pte_t pte;
|
||||
|
||||
if (home == PAGE_HOME_UNCACHED)
|
||||
return;
|
||||
local_irq_save(flags);
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
va = __fix_to_virt(FIX_KMAP_BEGIN + kmap_atomic_idx_push() +
|
||||
(KM_TYPE_NR * smp_processor_id()));
|
||||
#else
|
||||
va = __fix_to_virt(FIX_HOMECACHE_BEGIN + smp_processor_id());
|
||||
#endif
|
||||
ptep = virt_to_pte(NULL, (unsigned long)va);
|
||||
pte = pfn_pte(page_to_pfn(page), PAGE_KERNEL);
|
||||
__set_pte(ptep, pte_set_home(pte, home));
|
||||
homecache_finv_page_va((void *)va, home);
|
||||
__pte_clear(ptep);
|
||||
hv_flush_page(va, PAGE_SIZE);
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
kmap_atomic_idx_pop();
|
||||
#endif
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static void homecache_finv_page_home(struct page *page, int home)
|
||||
{
|
||||
if (!PageHighMem(page) && home == page_home(page))
|
||||
homecache_finv_page_va(page_address(page), home);
|
||||
else
|
||||
homecache_finv_map_page(page, home);
|
||||
}
|
||||
|
||||
static inline bool incoherent_home(int home)
|
||||
{
|
||||
return home == PAGE_HOME_IMMUTABLE || home == PAGE_HOME_INCOHERENT;
|
||||
}
|
||||
|
||||
static void homecache_finv_page_internal(struct page *page, int force_map)
|
||||
{
|
||||
int home = page_home(page);
|
||||
if (home == PAGE_HOME_UNCACHED)
|
||||
return;
|
||||
if (incoherent_home(home)) {
|
||||
int cpu;
|
||||
for_each_cpu(cpu, &cpu_cacheable_map)
|
||||
homecache_finv_map_page(page, cpu);
|
||||
} else if (force_map) {
|
||||
/* Force if, e.g., the normal mapping is migrating. */
|
||||
homecache_finv_map_page(page, home);
|
||||
} else {
|
||||
homecache_finv_page_home(page, home);
|
||||
}
|
||||
sim_validate_lines_evicted(PFN_PHYS(page_to_pfn(page)), PAGE_SIZE);
|
||||
}
|
||||
|
||||
void homecache_finv_page(struct page *page)
|
||||
{
|
||||
homecache_finv_page_internal(page, 0);
|
||||
}
|
||||
|
||||
void homecache_evict(const struct cpumask *mask)
|
||||
{
|
||||
flush_remote(0, HV_FLUSH_EVICT_L2, mask, 0, 0, 0, NULL, NULL, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Return a mask of the cpus whose caches currently own these pages.
|
||||
* The return value is whether the pages are all coherently cached
|
||||
* (i.e. none are immutable, incoherent, or uncached).
|
||||
*/
|
||||
static int homecache_mask(struct page *page, int pages,
|
||||
struct cpumask *home_mask)
|
||||
{
|
||||
int i;
|
||||
int cached_coherently = 1;
|
||||
cpumask_clear(home_mask);
|
||||
for (i = 0; i < pages; ++i) {
|
||||
int home = page_home(&page[i]);
|
||||
if (home == PAGE_HOME_IMMUTABLE ||
|
||||
home == PAGE_HOME_INCOHERENT) {
|
||||
cpumask_copy(home_mask, cpu_possible_mask);
|
||||
return 0;
|
||||
}
|
||||
#if CHIP_HAS_CBOX_HOME_MAP()
|
||||
if (home == PAGE_HOME_HASH) {
|
||||
cpumask_or(home_mask, home_mask, &hash_for_home_map);
|
||||
continue;
|
||||
}
|
||||
#endif
|
||||
if (home == PAGE_HOME_UNCACHED) {
|
||||
cached_coherently = 0;
|
||||
continue;
|
||||
}
|
||||
BUG_ON(home < 0 || home >= NR_CPUS);
|
||||
cpumask_set_cpu(home, home_mask);
|
||||
}
|
||||
return cached_coherently;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the passed length, or zero if it's long enough that we
|
||||
* believe we should evict the whole L2 cache.
|
||||
*/
|
||||
static unsigned long cache_flush_length(unsigned long length)
|
||||
{
|
||||
return (length >= CHIP_L2_CACHE_SIZE()) ? HV_FLUSH_EVICT_L2 : length;
|
||||
}
|
||||
|
||||
/* Flush a page out of whatever cache(s) it is in. */
|
||||
void homecache_flush_cache(struct page *page, int order)
|
||||
{
|
||||
int pages = 1 << order;
|
||||
int length = cache_flush_length(pages * PAGE_SIZE);
|
||||
unsigned long pfn = page_to_pfn(page);
|
||||
struct cpumask home_mask;
|
||||
|
||||
homecache_mask(page, pages, &home_mask);
|
||||
flush_remote(pfn, length, &home_mask, 0, 0, 0, NULL, NULL, 0);
|
||||
sim_validate_lines_evicted(PFN_PHYS(pfn), pages * PAGE_SIZE);
|
||||
}
|
||||
|
||||
|
||||
/* Report the home corresponding to a given PTE. */
|
||||
static int pte_to_home(pte_t pte)
|
||||
{
|
||||
@ -441,15 +432,8 @@ struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
|
||||
return page;
|
||||
}
|
||||
|
||||
void homecache_free_pages(unsigned long addr, unsigned int order)
|
||||
void __homecache_free_pages(struct page *page, unsigned int order)
|
||||
{
|
||||
struct page *page;
|
||||
|
||||
if (addr == 0)
|
||||
return;
|
||||
|
||||
VM_BUG_ON(!virt_addr_valid((void *)addr));
|
||||
page = virt_to_page((void *)addr);
|
||||
if (put_page_testzero(page)) {
|
||||
homecache_change_page_home(page, order, initial_page_home());
|
||||
if (order == 0) {
|
||||
@ -460,3 +444,13 @@ void homecache_free_pages(unsigned long addr, unsigned int order)
|
||||
}
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(__homecache_free_pages);
|
||||
|
||||
void homecache_free_pages(unsigned long addr, unsigned int order)
|
||||
{
|
||||
if (addr != 0) {
|
||||
VM_BUG_ON(!virt_addr_valid((void *)addr));
|
||||
__homecache_free_pages(virt_to_page((void *)addr), order);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(homecache_free_pages);
|
||||
|
||||
@ -150,7 +150,21 @@ void __init shatter_pmd(pmd_t *pmd)
|
||||
assign_pte(pmd, pte);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
#ifdef __tilegx__
|
||||
static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
|
||||
{
|
||||
pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va);
|
||||
if (pud_none(*pud))
|
||||
assign_pmd(pud, alloc_pmd());
|
||||
return pmd_offset(pud, va);
|
||||
}
|
||||
#else
|
||||
static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
|
||||
{
|
||||
return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This function initializes a certain range of kernel virtual memory
|
||||
* with new bootmem page tables, everywhere page tables are missing in
|
||||
@ -163,24 +177,17 @@ void __init shatter_pmd(pmd_t *pmd)
|
||||
* checking the pgd every time.
|
||||
*/
|
||||
static void __init page_table_range_init(unsigned long start,
|
||||
unsigned long end, pgd_t *pgd_base)
|
||||
unsigned long end, pgd_t *pgd)
|
||||
{
|
||||
pgd_t *pgd;
|
||||
int pgd_idx;
|
||||
unsigned long vaddr;
|
||||
|
||||
vaddr = start;
|
||||
pgd_idx = pgd_index(vaddr);
|
||||
pgd = pgd_base + pgd_idx;
|
||||
|
||||
for ( ; (pgd_idx < PTRS_PER_PGD) && (vaddr != end); pgd++, pgd_idx++) {
|
||||
pmd_t *pmd = pmd_offset(pud_offset(pgd, vaddr), vaddr);
|
||||
start = round_down(start, PMD_SIZE);
|
||||
end = round_up(end, PMD_SIZE);
|
||||
for (vaddr = start; vaddr < end; vaddr += PMD_SIZE) {
|
||||
pmd_t *pmd = get_pmd(pgd, vaddr);
|
||||
if (pmd_none(*pmd))
|
||||
assign_pte(pmd, alloc_pte());
|
||||
vaddr += PMD_SIZE;
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_HIGHMEM */
|
||||
|
||||
|
||||
#if CHIP_HAS_CBOX_HOME_MAP()
|
||||
@ -404,21 +411,6 @@ static inline pgprot_t ktext_set_nocache(pgprot_t prot)
|
||||
return prot;
|
||||
}
|
||||
|
||||
#ifndef __tilegx__
|
||||
static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
|
||||
{
|
||||
return pmd_offset(pud_offset(&pgtables[pgd_index(va)], va), va);
|
||||
}
|
||||
#else
|
||||
static pmd_t *__init get_pmd(pgd_t pgtables[], unsigned long va)
|
||||
{
|
||||
pud_t *pud = pud_offset(&pgtables[pgd_index(va)], va);
|
||||
if (pud_none(*pud))
|
||||
assign_pmd(pud, alloc_pmd());
|
||||
return pmd_offset(pud, va);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Temporary page table we use for staging. */
|
||||
static pgd_t pgtables[PTRS_PER_PGD]
|
||||
__attribute__((aligned(HV_PAGE_TABLE_ALIGN)));
|
||||
@ -779,9 +771,6 @@ static void __init set_non_bootmem_pages_init(void)
|
||||
*/
|
||||
void __init paging_init(void)
|
||||
{
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
unsigned long vaddr, end;
|
||||
#endif
|
||||
#ifdef __tilegx__
|
||||
pud_t *pud;
|
||||
#endif
|
||||
@ -789,14 +778,14 @@ void __init paging_init(void)
|
||||
|
||||
kernel_physical_mapping_init(pgd_base);
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
/*
|
||||
* Fixed mappings, only the page table structure has to be
|
||||
* created - mappings will be set by set_fixmap():
|
||||
*/
|
||||
vaddr = __fix_to_virt(__end_of_fixed_addresses - 1) & PMD_MASK;
|
||||
end = (FIXADDR_TOP + PMD_SIZE - 1) & PMD_MASK;
|
||||
page_table_range_init(vaddr, end, pgd_base);
|
||||
page_table_range_init(fix_to_virt(__end_of_fixed_addresses - 1),
|
||||
FIXADDR_TOP, pgd_base);
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
permanent_kmaps_init(pgd_base);
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user