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Merge branch 'intel-wired-lan-driver-fixes-2024-10-21-igb-ice'

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Jacob Keller says:

====================
Intel Wired LAN Driver Fixes 2024-10-21 (igb, ice)

This series includes fixes for the ice and igb drivers.

Wander fixes an issue in igb when operating on PREEMPT_RT kernels due to
the PREEMPT_RT kernel switching IRQs to be threaded by default.

Michal fixes the ice driver to block subfunction port creation when the PF
is operating in legacy (non-switchdev) mode.

Arkadiusz fixes a crash when loading the ice driver on an E810 LOM which
has DPLL enabled.

Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
====================

Link: https://patch.msgid.link/20241021-iwl-2024-10-21-iwl-net-fixes-v1-0-a50cb3059f55@intel.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni 2024-10-29 15:24:55 +01:00
commit bacccddbbc
5 changed files with 97 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/net/ethernet/intel/ice/devlink/devlink_port.c
View File

@ -989,5 +989,11 @@ ice_devlink_port_new(struct devlink *devlink,
if (err)
return err;
if (!ice_is_eswitch_mode_switchdev(pf)) {
NL_SET_ERR_MSG_MOD(extack,
"SF ports are only supported in eswitch switchdev mode");
return -EOPNOTSUPP;
}
return ice_alloc_dynamic_port(pf, new_attr, extack, devlink_port);
}

70
drivers/net/ethernet/intel/ice/ice_dpll.c
View File

@ -10,6 +10,7 @@
#define ICE_DPLL_PIN_IDX_INVALID 0xff
#define ICE_DPLL_RCLK_NUM_PER_PF 1
#define ICE_DPLL_PIN_ESYNC_PULSE_HIGH_PERCENT 25
#define ICE_DPLL_PIN_GEN_RCLK_FREQ 1953125
/**
* enum ice_dpll_pin_type - enumerate ice pin types:
@ -2063,6 +2064,73 @@ static int ice_dpll_init_worker(struct ice_pf *pf)
return 0;
}
/**
* ice_dpll_init_info_pins_generic - initializes generic pins info
* @pf: board private structure
* @input: if input pins initialized
*
* Init information for generic pins, cache them in PF's pins structures.
*
* Return:
* * 0 - success
* * negative - init failure reason
*/
static int ice_dpll_init_info_pins_generic(struct ice_pf *pf, bool input)
{
struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps;
static const char labels[][sizeof("99")] = {
"0", "1", "2", "3", "4", "5", "6", "7", "8",
"9", "10", "11", "12", "13", "14", "15" };
u32 cap = DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
enum ice_dpll_pin_type pin_type;
int i, pin_num, ret = -EINVAL;
struct ice_dpll_pin *pins;
u32 phase_adj_max;
if (input) {
pin_num = pf->dplls.num_inputs;
pins = pf->dplls.inputs;
phase_adj_max = pf->dplls.input_phase_adj_max;
pin_type = ICE_DPLL_PIN_TYPE_INPUT;
cap |= DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE;
} else {
pin_num = pf->dplls.num_outputs;
pins = pf->dplls.outputs;
phase_adj_max = pf->dplls.output_phase_adj_max;
pin_type = ICE_DPLL_PIN_TYPE_OUTPUT;
}
if (pin_num > ARRAY_SIZE(labels))
return ret;
for (i = 0; i < pin_num; i++) {
pins[i].idx = i;
pins[i].prop.board_label = labels[i];
pins[i].prop.phase_range.min = phase_adj_max;
pins[i].prop.phase_range.max = -phase_adj_max;
pins[i].prop.capabilities = cap;
pins[i].pf = pf;
ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL);
if (ret)
break;
if (input && pins[i].freq == ICE_DPLL_PIN_GEN_RCLK_FREQ)
pins[i].prop.type = DPLL_PIN_TYPE_MUX;
else
pins[i].prop.type = DPLL_PIN_TYPE_EXT;
if (!input)
continue;
ret = ice_aq_get_cgu_ref_prio(&pf->hw, de->dpll_idx, i,
&de->input_prio[i]);
if (ret)
break;
ret = ice_aq_get_cgu_ref_prio(&pf->hw, dp->dpll_idx, i,
&dp->input_prio[i]);
if (ret)
break;
}
return ret;
}
/**
* ice_dpll_init_info_direct_pins - initializes direct pins info
* @pf: board private structure
@ -2101,6 +2169,8 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf,
default:
return -EINVAL;
}
if (num_pins != ice_cgu_get_num_pins(hw, input))
return ice_dpll_init_info_pins_generic(pf, input);
for (i = 0; i < num_pins; i++) {
caps = 0;

21
drivers/net/ethernet/intel/ice/ice_ptp_hw.c
View File

@ -34,7 +34,6 @@ static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_inputs[] = {
ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
{ "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
{ "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, 0, },
};
static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
@ -52,7 +51,6 @@ static const struct ice_cgu_pin_desc ice_e810t_qsfp_cgu_inputs[] = {
ARRAY_SIZE(ice_cgu_pin_freq_common), ice_cgu_pin_freq_common },
{ "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
ARRAY_SIZE(ice_cgu_pin_freq_1_hz), ice_cgu_pin_freq_1_hz },
{ "OCXO", ZL_REF4N, DPLL_PIN_TYPE_INT_OSCILLATOR, },
};
static const struct ice_cgu_pin_desc ice_e810t_sfp_cgu_outputs[] = {
@ -5964,6 +5962,25 @@ ice_cgu_get_pin_desc(struct ice_hw *hw, bool input, int *size)
return t;
}
/**
* ice_cgu_get_num_pins - get pin description array size
* @hw: pointer to the hw struct
* @input: if request is done against input or output pins
*
* Return: size of pin description array for given hw.
*/
int ice_cgu_get_num_pins(struct ice_hw *hw, bool input)
{
const struct ice_cgu_pin_desc *t;
int size;
t = ice_cgu_get_pin_desc(hw, input, &size);
if (t)
return size;
return 0;
}
/**
* ice_cgu_get_pin_type - get pin's type
* @hw: pointer to the hw struct

1
drivers/net/ethernet/intel/ice/ice_ptp_hw.h
View File

@ -404,6 +404,7 @@ int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
bool ice_is_pca9575_present(struct ice_hw *hw);
int ice_cgu_get_num_pins(struct ice_hw *hw, bool input);
enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
struct dpll_pin_frequency *
ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);

2
drivers/net/ethernet/intel/igb/igb_main.c
View File

@ -907,7 +907,7 @@ static int igb_request_msix(struct igb_adapter *adapter)
int i, err = 0, vector = 0, free_vector = 0;
err = request_irq(adapter->msix_entries[vector].vector,
igb_msix_other, 0, netdev->name, adapter);
igb_msix_other, IRQF_NO_THREAD, netdev->name, adapter);
if (err)
goto err_out;