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EDAC/i10nm: Add Intel Granite Rapids server support
The Granite Rapids CPU model uses similar memory controller registers as Sapphire Rapids server but with some different configurations: - Various memory controller numbers for different Granite Rapids CPUs. So detect the number of present memory controllers at run time. - Different MMIO offsets of memory controllers. - Different triples of bus/dev/fun of some PCI devices used in i10nm_edac. Add above configurations and Granite Rapids CPU model ID for EDAC support. [Tony: Fixed 2 typos s/strcture/structure/] Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com> Link: https://lore.kernel.org/all/20230113032802.41752-1-qiuxu.zhuo@intel.com
This commit is contained in:
Qiuxu Zhuo
Tony Luck
parent
dd7814b785
commit
ba987eaaab
@ -13,7 +13,7 @@
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#include "edac_module.h"
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#include "skx_common.h"
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#define I10NM_REVISION "v0.0.5"
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#define I10NM_REVISION "v0.0.6"
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#define EDAC_MOD_STR "i10nm_edac"
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/* Debug macros */
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@ -22,25 +22,34 @@
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#define I10NM_GET_SCK_BAR(d, reg) \
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pci_read_config_dword((d)->uracu, 0xd0, &(reg))
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#define I10NM_GET_IMC_BAR(d, i, reg) \
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pci_read_config_dword((d)->uracu, 0xd8 + (i) * 4, &(reg))
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#define I10NM_GET_IMC_BAR(d, i, reg) \
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pci_read_config_dword((d)->uracu, \
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(res_cfg->type == GNR ? 0xd4 : 0xd8) + (i) * 4, &(reg))
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#define I10NM_GET_SAD(d, offset, i, reg)\
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pci_read_config_dword((d)->sad_all, (offset) + (i) * 8, &(reg))
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pci_read_config_dword((d)->sad_all, (offset) + (i) * \
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(res_cfg->type == GNR ? 12 : 8), &(reg))
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#define I10NM_GET_HBM_IMC_BAR(d, reg) \
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pci_read_config_dword((d)->uracu, 0xd4, &(reg))
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#define I10NM_GET_CAPID3_CFG(d, reg) \
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pci_read_config_dword((d)->pcu_cr3, 0x90, &(reg))
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pci_read_config_dword((d)->pcu_cr3, \
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res_cfg->type == GNR ? 0x290 : 0x90, &(reg))
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#define I10NM_GET_CAPID5_CFG(d, reg) \
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pci_read_config_dword((d)->pcu_cr3, \
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res_cfg->type == GNR ? 0x298 : 0x98, &(reg))
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#define I10NM_GET_DIMMMTR(m, i, j) \
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readl((m)->mbase + ((m)->hbm_mc ? 0x80c : 0x2080c) + \
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readl((m)->mbase + ((m)->hbm_mc ? 0x80c : \
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(res_cfg->type == GNR ? 0xc0c : 0x2080c)) + \
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(i) * (m)->chan_mmio_sz + (j) * 4)
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#define I10NM_GET_MCDDRTCFG(m, i) \
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readl((m)->mbase + ((m)->hbm_mc ? 0x970 : 0x20970) + \
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(i) * (m)->chan_mmio_sz)
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#define I10NM_GET_MCMTR(m, i) \
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readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : 0x20ef8) + \
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readl((m)->mbase + ((m)->hbm_mc ? 0xef8 : \
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(res_cfg->type == GNR ? 0xaf8 : 0x20ef8)) + \
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(i) * (m)->chan_mmio_sz)
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#define I10NM_GET_AMAP(m, i) \
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readl((m)->mbase + ((m)->hbm_mc ? 0x814 : 0x20814) + \
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readl((m)->mbase + ((m)->hbm_mc ? 0x814 : \
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(res_cfg->type == GNR ? 0xc14 : 0x20814)) + \
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(i) * (m)->chan_mmio_sz)
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#define I10NM_GET_REG32(m, i, offset) \
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readl((m)->mbase + (i) * (m)->chan_mmio_sz + (offset))
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@ -56,7 +65,10 @@
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#define I10NM_GET_HBM_IMC_MMIO_OFFSET(reg) \
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((GET_BITFIELD(reg, 0, 10) << 12) + 0x140000)
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#define I10NM_GNR_IMC_MMIO_OFFSET 0x24c000
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#define I10NM_GNR_IMC_MMIO_SIZE 0x4000
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#define I10NM_HBM_IMC_MMIO_SIZE 0x9000
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#define I10NM_DDR_IMC_CH_CNT(reg) GET_BITFIELD(reg, 21, 24)
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#define I10NM_IS_HBM_PRESENT(reg) GET_BITFIELD(reg, 27, 30)
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#define I10NM_IS_HBM_IMC(reg) GET_BITFIELD(reg, 29, 29)
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@ -323,6 +335,79 @@ static struct pci_dev *pci_get_dev_wrapper(int dom, unsigned int bus,
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return pdev;
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}
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/**
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* i10nm_get_imc_num() - Get the number of present DDR memory controllers.
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*
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* @cfg : The pointer to the structure of EDAC resource configurations.
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*
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* For Granite Rapids CPUs, the number of present DDR memory controllers read
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* at runtime overwrites the value statically configured in @cfg->ddr_imc_num.
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* For other CPUs, the number of present DDR memory controllers is statically
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* configured in @cfg->ddr_imc_num.
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*
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* RETURNS : 0 on success, < 0 on failure.
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*/
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static int i10nm_get_imc_num(struct res_config *cfg)
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{
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int n, imc_num, chan_num = 0;
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struct skx_dev *d;
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u32 reg;
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list_for_each_entry(d, i10nm_edac_list, list) {
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d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->pcu_cr3_bdf.bus],
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res_cfg->pcu_cr3_bdf.dev,
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res_cfg->pcu_cr3_bdf.fun);
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if (!d->pcu_cr3)
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continue;
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if (I10NM_GET_CAPID5_CFG(d, reg))
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continue;
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n = I10NM_DDR_IMC_CH_CNT(reg);
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if (!chan_num) {
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chan_num = n;
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edac_dbg(2, "Get DDR CH number: %d\n", chan_num);
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} else if (chan_num != n) {
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i10nm_printk(KERN_NOTICE, "Get DDR CH numbers: %d, %d\n", chan_num, n);
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}
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}
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switch (cfg->type) {
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case GNR:
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/*
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* One channel per DDR memory controller for Granite Rapids CPUs.
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*/
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imc_num = chan_num;
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if (!imc_num) {
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i10nm_printk(KERN_ERR, "Invalid DDR MC number\n");
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return -ENODEV;
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}
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if (imc_num > I10NM_NUM_DDR_IMC) {
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i10nm_printk(KERN_ERR, "Need to make I10NM_NUM_DDR_IMC >= %d\n", imc_num);
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return -EINVAL;
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}
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if (cfg->ddr_imc_num != imc_num) {
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/*
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* Store the number of present DDR memory controllers.
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*/
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cfg->ddr_imc_num = imc_num;
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edac_dbg(2, "Set DDR MC number: %d", imc_num);
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}
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return 0;
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default:
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/*
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* For other CPUs, the number of present DDR memory controllers
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* is statically pre-configured in cfg->ddr_imc_num.
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*/
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return 0;
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}
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}
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static bool i10nm_check_2lm(struct res_config *cfg)
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{
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struct skx_dev *d;
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@ -445,6 +530,98 @@ static bool i10nm_mc_decode(struct decoded_addr *res)
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return true;
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}
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/**
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* get_gnr_mdev() - Get the PCI device of the @logical_idx-th DDR memory controller.
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*
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* @d : The pointer to the structure of CPU socket EDAC device.
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* @logical_idx : The logical index of the present memory controller (0 ~ max present MC# - 1).
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* @physical_idx : To store the corresponding physical index of @logical_idx.
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*
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* RETURNS : The PCI device of the @logical_idx-th DDR memory controller, NULL on failure.
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*/
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static struct pci_dev *get_gnr_mdev(struct skx_dev *d, int logical_idx, int *physical_idx)
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{
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#define GNR_MAX_IMC_PCI_CNT 28
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struct pci_dev *mdev;
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int i, logical = 0;
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/*
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* Detect present memory controllers from { PCI device: 8-5, function 7-1 }
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*/
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for (i = 0; i < GNR_MAX_IMC_PCI_CNT; i++) {
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mdev = pci_get_dev_wrapper(d->seg,
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d->bus[res_cfg->ddr_mdev_bdf.bus],
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res_cfg->ddr_mdev_bdf.dev + i / 7,
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res_cfg->ddr_mdev_bdf.fun + i % 7);
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if (mdev) {
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if (logical == logical_idx) {
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*physical_idx = i;
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return mdev;
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}
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pci_dev_put(mdev);
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logical++;
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}
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}
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return NULL;
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}
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/**
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* get_ddr_munit() - Get the resource of the i-th DDR memory controller.
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*
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* @d : The pointer to the structure of CPU socket EDAC device.
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* @i : The index of the CPU socket relative DDR memory controller.
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* @offset : To store the MMIO offset of the i-th DDR memory controller.
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* @size : To store the MMIO size of the i-th DDR memory controller.
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*
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* RETURNS : The PCI device of the i-th DDR memory controller, NULL on failure.
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*/
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static struct pci_dev *get_ddr_munit(struct skx_dev *d, int i, u32 *offset, unsigned long *size)
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{
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struct pci_dev *mdev;
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int physical_idx;
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u32 reg;
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switch (res_cfg->type) {
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case GNR:
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if (I10NM_GET_IMC_BAR(d, 0, reg)) {
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i10nm_printk(KERN_ERR, "Failed to get mc0 bar\n");
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return NULL;
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}
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mdev = get_gnr_mdev(d, i, &physical_idx);
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if (!mdev)
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return NULL;
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*offset = I10NM_GET_IMC_MMIO_OFFSET(reg) +
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I10NM_GNR_IMC_MMIO_OFFSET +
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physical_idx * I10NM_GNR_IMC_MMIO_SIZE;
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*size = I10NM_GNR_IMC_MMIO_SIZE;
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break;
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default:
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if (I10NM_GET_IMC_BAR(d, i, reg)) {
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i10nm_printk(KERN_ERR, "Failed to get mc%d bar\n", i);
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return NULL;
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}
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mdev = pci_get_dev_wrapper(d->seg,
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d->bus[res_cfg->ddr_mdev_bdf.bus],
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res_cfg->ddr_mdev_bdf.dev + i,
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res_cfg->ddr_mdev_bdf.fun);
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if (!mdev)
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return NULL;
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*offset = I10NM_GET_IMC_MMIO_OFFSET(reg);
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*size = I10NM_GET_IMC_MMIO_SIZE(reg);
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}
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return mdev;
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}
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static int i10nm_get_ddr_munits(void)
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{
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struct pci_dev *mdev;
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@ -478,9 +655,8 @@ static int i10nm_get_ddr_munits(void)
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j++, base, reg);
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for (i = 0; i < res_cfg->ddr_imc_num; i++) {
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mdev = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->ddr_mdev_bdf.bus],
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res_cfg->ddr_mdev_bdf.dev + i,
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res_cfg->ddr_mdev_bdf.fun);
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mdev = get_ddr_munit(d, i, &off, &size);
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if (i == 0 && !mdev) {
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i10nm_printk(KERN_ERR, "No IMC found\n");
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return -ENODEV;
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@ -490,13 +666,6 @@ static int i10nm_get_ddr_munits(void)
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d->imc[i].mdev = mdev;
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if (I10NM_GET_IMC_BAR(d, i, reg)) {
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i10nm_printk(KERN_ERR, "Failed to get mc bar\n");
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return -ENODEV;
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}
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off = I10NM_GET_IMC_MMIO_OFFSET(reg);
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size = I10NM_GET_IMC_MMIO_SIZE(reg);
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edac_dbg(2, "mc%d mmio base 0x%llx size 0x%lx (reg 0x%x)\n",
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i, base + off, size, reg);
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@ -536,9 +705,6 @@ static int i10nm_get_hbm_munits(void)
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u64 base;
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list_for_each_entry(d, i10nm_edac_list, list) {
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d->pcu_cr3 = pci_get_dev_wrapper(d->seg, d->bus[res_cfg->pcu_cr3_bdf.bus],
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res_cfg->pcu_cr3_bdf.dev,
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res_cfg->pcu_cr3_bdf.fun);
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if (!d->pcu_cr3)
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return -ENODEV;
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@ -678,6 +844,23 @@ static struct res_config spr_cfg = {
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.offsets_demand_hbm1 = offsets_demand_spr_hbm1,
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};
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static struct res_config gnr_cfg = {
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.type = GNR,
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.decs_did = 0x3252,
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.busno_cfg_offset = 0xd0,
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.ddr_imc_num = 12,
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.ddr_chan_num = 1,
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.ddr_dimm_num = 2,
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.ddr_chan_mmio_sz = 0x4000,
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.support_ddr5 = true,
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.sad_all_bdf = {0, 13, 0},
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.pcu_cr3_bdf = {0, 5, 0},
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.util_all_bdf = {0, 13, 1},
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.uracu_bdf = {0, 0, 1},
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.ddr_mdev_bdf = {0, 5, 1},
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.sad_all_offset = 0x300,
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};
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static const struct x86_cpu_id i10nm_cpuids[] = {
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X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x0, 0x3), &i10nm_cfg0),
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X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ATOM_TREMONT_D, X86_STEPPINGS(0x4, 0xf), &i10nm_cfg1),
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@ -686,6 +869,7 @@ static const struct x86_cpu_id i10nm_cpuids[] = {
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X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(ICELAKE_D, X86_STEPPINGS(0x0, 0xf), &i10nm_cfg1),
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X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SAPPHIRERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg),
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X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(EMERALDRAPIDS_X, X86_STEPPINGS(0x0, 0xf), &spr_cfg),
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X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(GRANITERAPIDS_X, X86_STEPPINGS(0x0, 0xf), &gnr_cfg),
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{}
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};
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MODULE_DEVICE_TABLE(x86cpu, i10nm_cpuids);
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@ -705,7 +889,7 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
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{
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struct skx_pvt *pvt = mci->pvt_info;
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struct skx_imc *imc = pvt->imc;
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u32 mtr, amap, mcddrtcfg;
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u32 mtr, amap, mcddrtcfg = 0;
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struct dimm_info *dimm;
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int i, j, ndimms;
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@ -715,7 +899,10 @@ static int i10nm_get_dimm_config(struct mem_ctl_info *mci,
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ndimms = 0;
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amap = I10NM_GET_AMAP(imc, i);
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mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
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if (res_cfg->type != GNR)
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mcddrtcfg = I10NM_GET_MCDDRTCFG(imc, i);
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for (j = 0; j < imc->num_dimms; j++) {
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dimm = edac_get_dimm(mci, i, j, 0);
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mtr = I10NM_GET_DIMMMTR(imc, i, j);
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@ -834,6 +1021,10 @@ static int __init i10nm_init(void)
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return -ENODEV;
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}
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rc = i10nm_get_imc_num(cfg);
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if (rc < 0)
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goto fail;
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mem_cfg_2lm = i10nm_check_2lm(cfg);
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skx_set_mem_cfg(mem_cfg_2lm);
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@ -33,7 +33,7 @@
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#define SKX_NUM_CHANNELS 3 /* Channels per memory controller */
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#define SKX_NUM_DIMMS 2 /* Max DIMMS per channel */
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#define I10NM_NUM_DDR_IMC 4
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#define I10NM_NUM_DDR_IMC 12
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#define I10NM_NUM_DDR_CHANNELS 2
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#define I10NM_NUM_DDR_DIMMS 2
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@ -129,7 +129,8 @@ struct skx_pvt {
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enum type {
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SKX,
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I10NM,
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SPR
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SPR,
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GNR
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};
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enum {
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