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clk: renesas: r8a7795: make SD clk definition specific for GEN3
About SD clocks: The clock type is Gen3 specific, the callbacks are all Gen3 specific; I think the clock definition should also be Gen3 specific and not in the general header file. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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@ -65,6 +65,9 @@ enum r8a7795_clk_types {
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CLK_TYPE_GEN3_SD,
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};
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#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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@ -102,10 +105,10 @@ static const struct cpg_core_clk r8a7795_core_clks[] __initconst = {
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DEF_FIXED("s3d2", R8A7795_CLK_S3D2, CLK_S3, 2, 1),
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DEF_FIXED("s3d4", R8A7795_CLK_S3D4, CLK_S3, 4, 1),
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DEF_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
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DEF_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
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DEF_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
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DEF_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
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DEF_GEN3_SD("sd0", R8A7795_CLK_SD0, CLK_PLL1_DIV2, 0x0074),
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DEF_GEN3_SD("sd1", R8A7795_CLK_SD1, CLK_PLL1_DIV2, 0x0078),
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DEF_GEN3_SD("sd2", R8A7795_CLK_SD2, CLK_PLL1_DIV2, 0x0268),
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DEF_GEN3_SD("sd3", R8A7795_CLK_SD3, CLK_PLL1_DIV2, 0x026c),
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DEF_FIXED("cl", R8A7795_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A7795_CLK_CP, CLK_EXTAL, 2, 1),
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@ -53,9 +53,6 @@ enum clk_types {
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DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
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#define DEF_DIV6P1(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
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#define DEF_SD(_name, _id, _parent, _offset) \
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DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
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/*
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* Definitions of Module Clocks
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