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drm/i915: move the wait_rendering call into flush_gpu_write_domain
One caller (for the pageflip support) wants a purely pipelined flush. Distinguish this case by a new parameter. This will also be useful later on for pipelined fencing. v2: Simplify the code by depending upon the implicit request emitting of i915_wait_request. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> [ickle: And drop the non-interruptible support in the process.] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
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@ -37,7 +37,9 @@
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#include <linux/intel-gtt.h>
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static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
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static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
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static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
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bool pipelined);
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static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
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static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
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@ -46,8 +48,7 @@ static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
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uint64_t offset,
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uint64_t size);
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static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
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static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
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bool interruptible);
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static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
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static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
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unsigned alignment);
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static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
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@ -1933,8 +1934,7 @@ i915_gem_flush(struct drm_device *dev,
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* safe to unbind from the GTT or access from the CPU.
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*/
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static int
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i915_gem_object_wait_rendering(struct drm_gem_object *obj,
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bool interruptible)
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i915_gem_object_wait_rendering(struct drm_gem_object *obj)
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{
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struct drm_device *dev = obj->dev;
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struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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@ -1953,10 +1953,9 @@ i915_gem_object_wait_rendering(struct drm_gem_object *obj,
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DRM_INFO("%s: object %p wait for seqno %08x\n",
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__func__, obj, obj_priv->last_rendering_seqno);
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#endif
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ret = i915_do_wait_request(dev,
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obj_priv->last_rendering_seqno,
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interruptible,
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obj_priv->ring);
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ret = i915_wait_request(dev,
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obj_priv->last_rendering_seqno,
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obj_priv->ring);
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if (ret != 0)
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return ret;
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}
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@ -2453,11 +2452,7 @@ i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
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if (!IS_I965G(dev)) {
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int ret;
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret != 0)
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return ret;
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ret = i915_gem_object_wait_rendering(obj, true);
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ret = i915_gem_object_flush_gpu_write_domain(obj, false);
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if (ret != 0)
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return ret;
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}
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@ -2609,11 +2604,11 @@ i915_gem_clflush_object(struct drm_gem_object *obj)
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/** Flushes any GPU write domain for the object if it's dirty. */
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static int
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i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
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i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
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bool pipelined)
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{
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struct drm_device *dev = obj->dev;
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uint32_t old_write_domain;
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struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
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return 0;
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@ -2621,13 +2616,15 @@ i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
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/* Queue the GPU write cache flushing we need. */
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old_write_domain = obj->write_domain;
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i915_gem_flush(dev, 0, obj->write_domain);
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if (i915_add_request(dev, NULL, obj_priv->ring) == 0)
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return -ENOMEM;
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trace_i915_gem_object_change_domain(obj,
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obj->read_domains,
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old_write_domain);
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return 0;
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if (pipelined)
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return 0;
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return i915_gem_object_wait_rendering(obj);
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}
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/** Flushes the GTT write domain for the object if it's dirty. */
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@ -2684,7 +2681,7 @@ i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
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i915_gem_object_flush_cpu_write_domain(obj);
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break;
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default:
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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ret = i915_gem_object_flush_gpu_write_domain(obj, true);
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break;
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}
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@ -2708,12 +2705,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
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if (obj_priv->gtt_space == NULL)
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return -EINVAL;
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret != 0)
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return ret;
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/* Wait on any GPU rendering and flushing to occur. */
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ret = i915_gem_object_wait_rendering(obj, true);
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ret = i915_gem_object_flush_gpu_write_domain(obj, false);
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if (ret != 0)
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return ret;
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@ -2723,8 +2715,13 @@ i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
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/* If we're writing through the GTT domain, then CPU and GPU caches
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* will need to be invalidated at next use.
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*/
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if (write)
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if (write) {
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ret = i915_gem_object_wait_rendering(obj);
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if (ret)
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return ret;
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obj->read_domains &= I915_GEM_DOMAIN_GTT;
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}
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i915_gem_object_flush_cpu_write_domain(obj);
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@ -2753,38 +2750,25 @@ int
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i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
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{
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struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
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uint32_t old_write_domain, old_read_domains;
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uint32_t old_read_domains;
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int ret;
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/* Not valid to be called on unbound objects. */
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if (obj_priv->gtt_space == NULL)
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return -EINVAL;
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret)
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return ret;
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/* Wait on any GPU rendering and flushing to occur. */
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ret = i915_gem_object_wait_rendering(obj, false);
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ret = i915_gem_object_flush_gpu_write_domain(obj, true);
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if (ret != 0)
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return ret;
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i915_gem_object_flush_cpu_write_domain(obj);
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old_write_domain = obj->write_domain;
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old_read_domains = obj->read_domains;
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/* It should now be out of any other write domains, and we can update
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* the domain values for our changes.
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*/
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BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
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obj->read_domains = I915_GEM_DOMAIN_GTT;
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obj->write_domain = I915_GEM_DOMAIN_GTT;
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obj_priv->dirty = 1;
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trace_i915_gem_object_change_domain(obj,
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old_read_domains,
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old_write_domain);
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obj->write_domain);
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return 0;
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}
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@ -2801,12 +2785,7 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
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uint32_t old_write_domain, old_read_domains;
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int ret;
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret)
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return ret;
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/* Wait on any GPU rendering and flushing to occur. */
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ret = i915_gem_object_wait_rendering(obj, true);
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ret = i915_gem_object_flush_gpu_write_domain(obj, false);
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if (ret != 0)
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return ret;
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@ -2836,6 +2815,10 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
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* need to be invalidated at next use.
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*/
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if (write) {
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ret = i915_gem_object_wait_rendering(obj);
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if (ret)
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return ret;
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obj->read_domains &= I915_GEM_DOMAIN_CPU;
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obj->write_domain = I915_GEM_DOMAIN_CPU;
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}
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@ -3094,12 +3077,7 @@ i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
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if (offset == 0 && size == obj->size)
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return i915_gem_object_set_to_cpu_domain(obj, 0);
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ret = i915_gem_object_flush_gpu_write_domain(obj);
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if (ret)
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return ret;
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/* Wait on any GPU rendering and flushing to occur. */
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ret = i915_gem_object_wait_rendering(obj, true);
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ret = i915_gem_object_flush_gpu_write_domain(obj, false);
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if (ret != 0)
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return ret;
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i915_gem_object_flush_gtt_write_domain(obj);
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