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drm/amdgpu: make pipeline sync be in same place v2
v2: directly return for 'if' case. Signed-off-by: Chunming Zhou <David1.Zhou@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1132,7 +1132,6 @@ struct amdgpu_job {
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void *owner;
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uint64_t fence_ctx; /* the fence_context this job uses */
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bool vm_needs_flush;
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bool need_pipeline_sync;
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unsigned vm_id;
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uint64_t vm_pd_addr;
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uint32_t gds_base, gds_size;
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@ -121,7 +121,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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{
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struct amdgpu_device *adev = ring->adev;
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struct amdgpu_ib *ib = &ibs[0];
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struct dma_fence *tmp;
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struct dma_fence *tmp = NULL;
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bool skip_preamble, need_ctx_switch;
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unsigned patch_offset = ~0;
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struct amdgpu_vm *vm;
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@ -163,8 +163,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
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}
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if (ring->funcs->emit_pipeline_sync && job &&
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(tmp = amdgpu_sync_get_fence(&job->sched_sync))) {
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job->need_pipeline_sync = true;
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((tmp = amdgpu_sync_get_fence(&job->sched_sync)) ||
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amdgpu_vm_need_pipeline_sync(ring, job))) {
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amdgpu_ring_emit_pipeline_sync(ring);
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dma_fence_put(tmp);
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}
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@ -57,7 +57,6 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
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(*job)->vm = vm;
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(*job)->ibs = (void *)&(*job)[1];
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(*job)->num_ibs = num_ibs;
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(*job)->need_pipeline_sync = false;
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amdgpu_sync_create(&(*job)->sync);
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amdgpu_sync_create(&(*job)->sched_sync);
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@ -694,6 +694,35 @@ static u64 amdgpu_vm_adjust_mc_addr(struct amdgpu_device *adev, u64 mc_addr)
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return addr;
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}
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bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
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struct amdgpu_job *job)
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{
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struct amdgpu_device *adev = ring->adev;
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unsigned vmhub = ring->funcs->vmhub;
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struct amdgpu_vm_id_manager *id_mgr = &adev->vm_manager.id_mgr[vmhub];
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struct amdgpu_vm_id *id;
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bool gds_switch_needed;
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bool vm_flush_needed = job->vm_needs_flush ||
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amdgpu_vm_ring_has_compute_vm_bug(ring);
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if (job->vm_id == 0)
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return false;
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id = &id_mgr->ids[job->vm_id];
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gds_switch_needed = ring->funcs->emit_gds_switch && (
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id->gds_base != job->gds_base ||
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id->gds_size != job->gds_size ||
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id->gws_base != job->gws_base ||
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id->gws_size != job->gws_size ||
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id->oa_base != job->oa_base ||
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id->oa_size != job->oa_size);
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if (amdgpu_vm_had_gpu_reset(adev, id))
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return true;
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if (!vm_flush_needed && !gds_switch_needed)
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return false;
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return true;
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}
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/**
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* amdgpu_vm_flush - hardware flush the vm
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*
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@ -732,9 +761,6 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job)
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if (ring->funcs->init_cond_exec)
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patch_offset = amdgpu_ring_init_cond_exec(ring);
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if (ring->funcs->emit_pipeline_sync && !job->need_pipeline_sync)
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amdgpu_ring_emit_pipeline_sync(ring);
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if (ring->funcs->emit_vm_flush && vm_flush_needed) {
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u64 pd_addr = amdgpu_vm_adjust_mc_addr(adev, job->vm_pd_addr);
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struct dma_fence *fence;
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@ -245,5 +245,7 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va);
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint64_t vm_size);
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int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
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bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
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struct amdgpu_job *job);
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#endif
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