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[POWERPC] Xilinx: of_serial support for Xilinx uart 16550.
The Xilinx 16550 uart core is not a standard 16550 because it uses word-based addressing rather than byte-based addressing. With additional properties it is compatible with the open firmware 'ns16550' compatible binding. This code updates the of_serial driver to handle the reg-offset and reg-shift properties to enable this core to be used. Signed-off-by: John Linn <john.linn@xilinx.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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@ -2601,6 +2601,17 @@ platforms are moved over to use the flattened-device-tree model.
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differ between different families. May be
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'virtex2p', 'virtex4', or 'virtex5'.
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vi) Xilinx Uart 16550
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Xilinx UART 16550 devices are very similar to the NS16550 but with
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different register spacing and an offset from the base address.
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Requred properties:
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- clock-frequency : Frequency of the clock input
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- reg-offset : A value of 3 is required
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- reg-shift : A value of 2 is required
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p) Freescale Synchronous Serial Interface
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The SSI is a serial device that communicates with audio codecs. It can
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@ -31,7 +31,8 @@ static int __devinit of_platform_serial_setup(struct of_device *ofdev,
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struct resource resource;
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struct device_node *np = ofdev->node;
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const unsigned int *clk, *spd;
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int ret;
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const u32 *prop;
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int ret, prop_size;
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memset(port, 0, sizeof *port);
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spd = of_get_property(np, "current-speed", NULL);
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@ -49,6 +50,17 @@ static int __devinit of_platform_serial_setup(struct of_device *ofdev,
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spin_lock_init(&port->lock);
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port->mapbase = resource.start;
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/* Check for shifted address mapping */
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prop = of_get_property(np, "reg-offset", &prop_size);
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if (prop && (prop_size == sizeof(u32)))
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port->mapbase += *prop;
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/* Check for registers offset within the devices address range */
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prop = of_get_property(np, "reg-shift", &prop_size);
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if (prop && (prop_size == sizeof(u32)))
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port->regshift = *prop;
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port->irq = irq_of_parse_and_map(np, 0);
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port->iotype = UPIO_MEM;
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port->type = type;
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