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ARM: mach-shmobile: extend clock definitions on sh7372
Add definitions for DV_CLKI and HDMI clocks, extend support for PLLC2 and some other clocks. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Guennadi Liakhovetski
Paul Mundt
parent
b3dd51a8a6
commit
b90884c886
@ -50,6 +50,10 @@
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR4 0xe6150140
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/* Platforms must set frequency on their DV_CLKI pin */
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struct clk dv_clki_clk = {
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};
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/* Fixed 32 KHz root clock from EXTALR pin */
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static struct clk r_clk = {
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.rate = 32768,
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@ -81,6 +85,12 @@ static struct clk_ops div2_clk_ops = {
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.recalc = div2_recalc,
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};
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/* Divide dv_clki by two */
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struct clk dv_clki_div2_clk = {
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.ops = &div2_clk_ops,
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.parent = &dv_clki_clk,
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};
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/* Divide extal1 by two */
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static struct clk extal1_div2_clk = {
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.ops = &div2_clk_ops,
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@ -135,30 +145,160 @@ static struct clk pllc1_div2_clk = {
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};
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/* PLLC2 */
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/* Indices are important - they are the actual src selecting values */
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static struct clk *pllc2_parent[] = {
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[0] = &extal1_div2_clk,
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[1] = &extal2_div2_clk,
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[2] = &dv_clki_div2_clk,
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};
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/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
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static struct cpufreq_frequency_table pllc2_freq_table[29];
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static void pllc2_table_rebuild(struct clk *clk)
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{
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int i;
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/* Initialise PLLC2 frequency table */
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for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
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pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
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pllc2_freq_table[i].index = i;
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}
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/* This is a special entry - switching PLL off makes it a repeater */
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pllc2_freq_table[i].frequency = clk->parent->rate;
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pllc2_freq_table[i].index = i;
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pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
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pllc2_freq_table[i].index = i;
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}
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static unsigned long pllc2_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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pllc2_table_rebuild(clk);
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/*
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* If the PLL is off, mult == 1, clk->rate will be updated in
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* pllc2_enable().
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*/
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if (__raw_readl(PLLC2CR) & (1 << 31))
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mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
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return clk->parent->rate * mult;
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}
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static long pllc2_round_rate(struct clk *clk, unsigned long rate)
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{
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return clk_rate_table_round(clk, clk->freq_table, rate);
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}
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static int pllc2_enable(struct clk *clk)
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{
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int i;
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__raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
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for (i = 0; i < 100; i++)
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if (__raw_readl(PLLC2CR) & 0x80000000) {
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clk->rate = pllc2_recalc(clk);
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return 0;
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}
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pr_err("%s(): timeout!\n", __func__);
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return -ETIMEDOUT;
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}
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static void pllc2_disable(struct clk *clk)
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{
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__raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
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}
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static int pllc2_set_rate(struct clk *clk,
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unsigned long rate, int algo_id)
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{
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unsigned long value;
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int idx;
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idx = clk_rate_table_find(clk, clk->freq_table, rate);
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if (idx < 0)
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return idx;
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if (rate == clk->parent->rate) {
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pllc2_disable(clk);
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return 0;
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}
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value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
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if (value & 0x80000000)
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pllc2_disable(clk);
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__raw_writel((value & ~0x80000000) | ((idx + 19) << 24), PLLC2CR);
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if (value & 0x80000000)
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return pllc2_enable(clk);
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return 0;
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}
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static int pllc2_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 value;
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int ret, i;
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if (!clk->parent_table || !clk->parent_num)
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return -EINVAL;
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/* Search the parent */
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for (i = 0; i < clk->parent_num; i++)
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if (clk->parent_table[i] == parent)
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break;
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if (i == clk->parent_num)
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return -ENODEV;
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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value = __raw_readl(PLLC2CR) & ~(3 << 6);
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__raw_writel(value | (i << 6), PLLC2CR);
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/* Rebiuld the frequency table */
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pllc2_table_rebuild(clk);
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return 0;
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}
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static struct clk_ops pllc2_clk_ops = {
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.recalc = pllc2_recalc,
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.round_rate = pllc2_round_rate,
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.set_rate = pllc2_set_rate,
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.enable = pllc2_enable,
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.disable = pllc2_disable,
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.set_parent = pllc2_set_parent,
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};
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static struct clk pllc2_clk = {
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struct clk pllc2_clk = {
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.ops = &pllc2_clk_ops,
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.flags = CLK_ENABLE_ON_INIT,
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.parent = &extal1_div2_clk,
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.freq_table = pllc2_freq_table,
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.parent_table = pllc2_parent,
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.parent_num = ARRAY_SIZE(pllc2_parent),
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};
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static struct clk *main_clks[] = {
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&dv_clki_clk,
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&r_clk,
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&sh7372_extal1_clk,
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&sh7372_extal2_clk,
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&dv_clki_div2_clk,
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&extal1_div2_clk,
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&extal2_div2_clk,
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&extal2_div4_clk,
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@ -219,7 +359,7 @@ static struct clk div4_clks[DIV4_NR] = {
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enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
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DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU,
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DIV6_VOU, DIV6_HDMI, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
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DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
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DIV6_NR };
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static struct clk div6_clks[DIV6_NR] = {
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@ -233,12 +373,26 @@ static struct clk div6_clks[DIV6_NR] = {
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[DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
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[DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
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[DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
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[DIV6_HDMI] = SH_CLK_DIV6(&pllc1_div2_clk, HDMICKCR, 0),
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[DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
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[DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
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[DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
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};
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enum { DIV6_HDMI, DIV6_REPARENT_NR };
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/* Indices are important - they are the actual src selecting values */
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static struct clk *hdmi_parent[] = {
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[0] = &pllc1_div2_clk,
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[1] = &pllc2_clk,
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[2] = &dv_clki_clk,
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[3] = NULL, /* pllc2_div4 not implemented yet */
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};
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static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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[DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
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hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
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};
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enum { MSTP001,
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MSTP131, MSTP130,
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MSTP129, MSTP128,
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@ -247,7 +401,7 @@ enum { MSTP001,
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MSTP223,
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MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
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MSTP329, MSTP328, MSTP323, MSTP322, MSTP314, MSTP313, MSTP312,
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MSTP415, MSTP410, MSTP411, MSTP406, MSTP403,
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MSTP415, MSTP413, MSTP411, MSTP410, MSTP406, MSTP403,
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MSTP_NR };
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#define MSTP(_parent, _reg, _bit, _flags) \
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@ -281,6 +435,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
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[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
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[MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
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[MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
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[MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
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[MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
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[MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
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@ -292,6 +447,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk),
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CLKDEV_CON_ID("r_clk", &r_clk),
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CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
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CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
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@ -331,7 +487,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
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CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
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CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
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CLKDEV_CON_ID("hdmi_clk", &div6_clks[DIV6_HDMI]),
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CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
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CLKDEV_CON_ID("dsit_clk", &div6_clks[DIV6_DSIT]),
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CLKDEV_CON_ID("dsi0p_clk", &div6_clks[DIV6_DSI0P]),
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CLKDEV_CON_ID("dsi1p_clk", &div6_clks[DIV6_DSI1P]),
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@ -366,11 +522,13 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
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CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
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CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
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CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
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CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
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CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
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CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
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CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
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CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
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{.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]},
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};
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void __init sh7372_clock_init(void)
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@ -386,6 +544,9 @@ void __init sh7372_clock_init(void)
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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if (!ret)
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ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR);
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
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@ -11,6 +11,8 @@
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#ifndef __ASM_SH7372_H__
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#define __ASM_SH7372_H__
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#include <linux/sh_clk.h>
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/*
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* Pin Function Controller:
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* GPIO_FN_xx - GPIO used to select pin function
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@ -455,4 +457,8 @@ enum {
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SHDMA_SLAVE_SDHI2_TX,
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};
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extern struct clk dv_clki_clk;
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extern struct clk dv_clki_div2_clk;
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extern struct clk pllc2_clk;
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#endif /* __ASM_SH7372_H__ */
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