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cpufreq: tegra186: Fix initial frequency
Commit 6cc3d0e9a0
("cpufreq: tegra186: add
CPUFREQ_NEED_INITIAL_FREQ_CHECK flag") fixed CPUFREQ support for
Tegra186 but as a consequence the following warnings are now seen on
boot ...
cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 0 KHz
cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed to: 2035200 KHz
cpufreq: cpufreq_online: CPU1: Running at unlisted freq: 0 KHz
cpufreq: cpufreq_online: CPU1: Unlisted initial frequency changed to: 2035200 KHz
cpufreq: cpufreq_online: CPU2: Running at unlisted freq: 0 KHz
cpufreq: cpufreq_online: CPU2: Unlisted initial frequency changed to: 2035200 KHz
cpufreq: cpufreq_online: CPU3: Running at unlisted freq: 0 KHz
cpufreq: cpufreq_online: CPU3: Unlisted initial frequency changed to: 2035200 KHz
cpufreq: cpufreq_online: CPU4: Running at unlisted freq: 0 KHz
cpufreq: cpufreq_online: CPU4: Unlisted initial frequency changed to: 2035200 KHz
cpufreq: cpufreq_online: CPU5: Running at unlisted freq: 0 KHz
cpufreq: cpufreq_online: CPU5: Unlisted initial frequency changed to: 2035200 KHz
Fix this by adding a 'get' callback for the Tegra186 CPUFREQ driver to
retrieve the current operating frequency for a given CPU. The 'get'
callback uses the current 'ndiv' value that is programmed to determine
that current operating frequency.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
[ Viresh: Return 0 on error ]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
parent
b1593e53f2
commit
b89c01c960
@ -14,6 +14,7 @@
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#define EDVD_CORE_VOLT_FREQ(core) (0x20 + (core) * 0x4)
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#define EDVD_CORE_VOLT_FREQ_F_SHIFT 0
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#define EDVD_CORE_VOLT_FREQ_F_MASK 0xffff
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#define EDVD_CORE_VOLT_FREQ_V_SHIFT 16
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struct tegra186_cpufreq_cluster_info {
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@ -91,10 +92,39 @@ static int tegra186_cpufreq_set_target(struct cpufreq_policy *policy,
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return 0;
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}
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static unsigned int tegra186_cpufreq_get(unsigned int cpu)
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{
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struct cpufreq_frequency_table *tbl;
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struct cpufreq_policy *policy;
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void __iomem *edvd_reg;
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unsigned int i, freq = 0;
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u32 ndiv;
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policy = cpufreq_cpu_get(cpu);
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if (!policy)
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return 0;
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tbl = policy->freq_table;
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edvd_reg = policy->driver_data;
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ndiv = readl(edvd_reg) & EDVD_CORE_VOLT_FREQ_F_MASK;
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for (i = 0; tbl[i].frequency != CPUFREQ_TABLE_END; i++) {
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if ((tbl[i].driver_data & EDVD_CORE_VOLT_FREQ_F_MASK) == ndiv) {
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freq = tbl[i].frequency;
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break;
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}
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}
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cpufreq_cpu_put(policy);
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return freq;
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}
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static struct cpufreq_driver tegra186_cpufreq_driver = {
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.name = "tegra186",
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.flags = CPUFREQ_STICKY | CPUFREQ_HAVE_GOVERNOR_PER_POLICY |
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CPUFREQ_NEED_INITIAL_FREQ_CHECK,
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.get = tegra186_cpufreq_get,
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.verify = cpufreq_generic_frequency_table_verify,
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.target_index = tegra186_cpufreq_set_target,
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.init = tegra186_cpufreq_init,
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