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ASoC: fsl_sai: Update Tx/Rx channel enable mask
Tx channel enable (TCE) / Rx channel enable (RCE) bits enable corresponding data channel for Tx/Rx operation. Because SAI supports up the 8 channels TCE/RCE occupy up the 8 bits inside TCR3/RCR3 registers we need to extend the mask to reflect this. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> Link: https://lore.kernel.org/r/20190806151214.6783-3-daniel.baluta@nxp.com Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -599,7 +599,8 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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int ret;
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regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
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regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
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FSL_SAI_CR3_TRCE_MASK,
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FSL_SAI_CR3_TRCE);
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ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
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@ -614,7 +615,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
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regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
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FSL_SAI_CR3_TRCE_MASK, 0);
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}
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static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
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@ -110,6 +110,7 @@
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/* SAI Transmit and Receive Configuration 3 Register */
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#define FSL_SAI_CR3_TRCE BIT(16)
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#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)
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#define FSL_SAI_CR3_WDFL(x) (x)
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#define FSL_SAI_CR3_WDFL_MASK 0x1f
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