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usb: dwc3: Support quirk for writing high-low order

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There's the limitation of Synopsys dwc3 controller with ERST programming in
supporting separate ERSTBA_HI and ERSTBA_LO programming. It's supported when
the ERSTBA is programmed ERSTBA_HI before ERSTBA_LO. But, writing operations
in xHCI is done low-high order following xHCI spec. xHCI specification 5.1
"Register Conventions" states that 64 bit registers should be written in
low-high order. Synopsys dwc3 needs workaround for high-low order. That's why
adding new quirk is needed to support this.

Signed-off-by: Daehwan Jung <dh10.jung@samsung.com>
Link: https://lore.kernel.org/r/1718019553-111939-2-git-send-email-dh10.jung@samsung.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Daehwan Jung 2024-06-10 20:39:11 +09:00 committed by Greg Kroah-Hartman
parent 2bc0bea11c
commit b7ec7fd632
1 changed files with 3 additions and 1 deletions
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4
drivers/usb/dwc3/host.c
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@ -126,7 +126,7 @@ out:
int dwc3_host_init(struct dwc3 *dwc) int dwc3_host_init(struct dwc3 *dwc)
{ {
struct property_entry props[5]; struct property_entry props[6];
struct platform_device *xhci; struct platform_device *xhci;
int ret, irq; int ret, irq;
int prop_idx = 0; int prop_idx = 0;
@ -162,6 +162,8 @@ int dwc3_host_init(struct dwc3 *dwc)
props[prop_idx++] = PROPERTY_ENTRY_BOOL("xhci-sg-trb-cache-size-quirk"); props[prop_idx++] = PROPERTY_ENTRY_BOOL("xhci-sg-trb-cache-size-quirk");
props[prop_idx++] = PROPERTY_ENTRY_BOOL("write-64-hi-lo-quirk");
if (dwc->usb3_lpm_capable) if (dwc->usb3_lpm_capable)
props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb3-lpm-capable"); props[prop_idx++] = PROPERTY_ENTRY_BOOL("usb3-lpm-capable");