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staging: ccree: move FIPS support to kernel infrastructure
The ccree driver had its own FIPS support, complete with a test harness comparable to crypto testmgr and an implementation which disables crypto functionality on FIPS test error detection, either in Linux or from TEE. This patch removes the duplication, while reimplementing the handling of TEE reported FIPS errors according to the kernel policy of inducing a panic in such an event. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gilad Ben-Yossef
Greg Kroah-Hartman
parent
07642a075f
commit
b7e607bf33
@ -23,12 +23,3 @@ config CRYPTO_DEV_CCREE
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Choose this if you wish to use hardware acceleration of
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cryptographic operations on the system REE.
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If unsure say Y.
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config CCREE_FIPS_SUPPORT
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bool "Turn on CryptoCell 7XX REE FIPS mode support"
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depends on CRYPTO_DEV_CCREE
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default n
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help
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Say 'Y' to enable support for FIPS compliant mode by the
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CCREE driver.
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If unsure say N.
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@ -1,3 +1,3 @@
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obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o
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ccree-y := ssi_driver.o ssi_sysfs.o ssi_buffer_mgr.o ssi_request_mgr.o ssi_cipher.o ssi_hash.o ssi_aead.o ssi_ivgen.o ssi_sram_mgr.o ssi_pm.o
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ccree-$(CCREE_FIPS_SUPPORT) += ssi_fips.o ssi_fips_ll.o ssi_fips_ext.o ssi_fips_local.o
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ccree-$(CONFIG_CRYPTO_FIPS) += ssi_fips.o
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@ -36,7 +36,6 @@
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#include "ssi_hash.h"
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#include "ssi_sysfs.h"
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#include "ssi_sram_mgr.h"
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#include "ssi_fips_local.h"
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#define template_aead template_u.aead
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@ -146,8 +145,6 @@ static int ssi_aead_init(struct crypto_aead *tfm)
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container_of(alg, struct ssi_crypto_alg, aead_alg);
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SSI_LOG_DEBUG("Initializing context @%p for %s\n", ctx, crypto_tfm_alg_name(&(tfm->base)));
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CHECK_AND_RETURN_UPON_FIPS_ERROR();
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/* Initialize modes in instance */
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ctx->cipher_mode = ssi_alg->cipher_mode;
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ctx->flow_mode = ssi_alg->flow_mode;
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@ -538,7 +535,6 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key, unsigned int keylen)
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SSI_LOG_DEBUG("Setting key in context @%p for %s. key=%p keylen=%u\n",
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ctx, crypto_tfm_alg_name(crypto_aead_tfm(tfm)), key, keylen);
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CHECK_AND_RETURN_UPON_FIPS_ERROR();
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/* STAT_PHASE_0: Init and sanity checks */
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if (ctx->auth_mode != DRV_HASH_NULL) { /* authenc() alg. */
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@ -654,7 +650,6 @@ static int ssi_aead_setauthsize(
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{
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struct ssi_aead_ctx *ctx = crypto_aead_ctx(authenc);
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CHECK_AND_RETURN_UPON_FIPS_ERROR();
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/* Unsupported auth. sizes */
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if ((authsize == 0) ||
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(authsize > crypto_aead_maxauthsize(authenc))) {
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@ -1946,7 +1941,6 @@ static int ssi_aead_process(struct aead_request *req, enum drv_crypto_direction
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SSI_LOG_DEBUG("%s context=%p req=%p iv=%p src=%p src_ofs=%d dst=%p dst_ofs=%d cryptolen=%d\n",
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((direct == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"), ctx, req, req->iv,
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sg_virt(req->src), req->src->offset, sg_virt(req->dst), req->dst->offset, req->cryptlen);
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CHECK_AND_RETURN_UPON_FIPS_ERROR();
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/* STAT_PHASE_0: Init and sanity checks */
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@ -23,6 +23,7 @@
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#include <crypto/aes.h>
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#include <crypto/ctr.h>
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#include <crypto/des.h>
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#include <crypto/xts.h>
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#include "ssi_config.h"
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#include "ssi_driver.h"
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@ -31,7 +32,6 @@
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#include "ssi_cipher.h"
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#include "ssi_request_mgr.h"
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#include "ssi_sysfs.h"
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#include "ssi_fips_local.h"
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#define MAX_ABLKCIPHER_SEQ_LEN 6
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@ -188,7 +188,6 @@ static int ssi_blkcipher_init(struct crypto_tfm *tfm)
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SSI_LOG_DEBUG("Initializing context @%p for %s\n", ctx_p,
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crypto_tfm_alg_name(tfm));
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CHECK_AND_RETURN_UPON_FIPS_ERROR();
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ctx_p->cipher_mode = ssi_alg->cipher_mode;
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ctx_p->flow_mode = ssi_alg->flow_mode;
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ctx_p->drvdata = ssi_alg->drvdata;
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@ -265,9 +264,8 @@ static const u8 zero_buff[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
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/* The function verifies that tdes keys are not weak.*/
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static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen)
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static int ssi_verify_3des_keys(const u8 *key, unsigned int keylen)
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{
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#ifdef CCREE_FIPS_SUPPORT
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struct tdes_keys *tdes_key = (struct tdes_keys *)key;
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/* verify key1 != key2 and key3 != key2*/
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@ -275,21 +273,6 @@ static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen)
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(memcmp((u8 *)tdes_key->key3, (u8 *)tdes_key->key2, sizeof(tdes_key->key3)) == 0))) {
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return -ENOEXEC;
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}
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#endif /* CCREE_FIPS_SUPPORT */
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return 0;
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}
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/* The function verifies that xts keys are not weak.*/
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static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen)
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{
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#ifdef CCREE_FIPS_SUPPORT
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/* Weak key is define as key that its first half (128/256 lsb) equals its second half (128/256 msb) */
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int singleKeySize = keylen >> 1;
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if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0))
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return -ENOEXEC;
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#endif /* CCREE_FIPS_SUPPORT */
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return 0;
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}
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@ -322,8 +305,6 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm,
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ctx_p, crypto_tfm_alg_name(tfm), keylen);
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dump_byte_array("key", (u8 *)key, keylen);
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CHECK_AND_RETURN_UPON_FIPS_ERROR();
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SSI_LOG_DEBUG("ssi_blkcipher_setkey: after FIPS check");
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/* STAT_PHASE_0: Init and sanity checks */
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@ -385,13 +366,13 @@ static int ssi_blkcipher_setkey(struct crypto_tfm *tfm,
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}
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}
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if ((ctx_p->cipher_mode == DRV_CIPHER_XTS) &&
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ssi_fips_verify_xts_keys(key, keylen) != 0) {
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xts_check_key(tfm, key, keylen) != 0) {
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SSI_LOG_DEBUG("ssi_blkcipher_setkey: weak XTS key");
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return -EINVAL;
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}
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if ((ctx_p->flow_mode == S_DIN_to_DES) &&
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(keylen == DES3_EDE_KEY_SIZE) &&
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ssi_fips_verify_3des_keys(key, keylen) != 0) {
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ssi_verify_3des_keys(key, keylen) != 0) {
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SSI_LOG_DEBUG("ssi_blkcipher_setkey: weak 3DES key");
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return -EINVAL;
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}
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@ -754,7 +735,6 @@ static int ssi_blkcipher_process(
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((direction == DRV_CRYPTO_DIRECTION_ENCRYPT) ? "Encrypt" : "Decrypt"),
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areq, info, nbytes);
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CHECK_AND_RETURN_UPON_FIPS_ERROR();
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/* STAT_PHASE_0: Init and sanity checks */
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/* TODO: check data length according to mode */
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@ -855,8 +835,6 @@ static void ssi_ablkcipher_complete(struct device *dev, void *ssi_req, void __io
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struct ssi_ablkcipher_ctx *ctx_p = crypto_ablkcipher_ctx(tfm);
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unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
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CHECK_AND_RETURN_VOID_UPON_FIPS_ERROR();
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ssi_blkcipher_complete(dev, ctx_p, req_ctx, areq->dst, areq->src,
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ivsize, areq, cc_base);
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}
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@ -71,7 +71,7 @@
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#include "ssi_ivgen.h"
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#include "ssi_sram_mgr.h"
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#include "ssi_pm.h"
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#include "ssi_fips_local.h"
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#include "ssi_fips.h"
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#ifdef DX_DUMP_BYTES
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void dump_byte_array(const char *name, const u8 *the_array, unsigned long size)
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@ -398,6 +398,12 @@ static int init_cc_resources(struct platform_device *plat_dev)
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goto init_cc_res_err;
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}
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/* If we got here and FIPS mode is enabled
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* it means all FIPS test passed, so let TEE
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* know we're good.
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*/
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cc_set_ree_fips_status(new_drvdata, true);
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return 0;
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init_cc_res_err:
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@ -48,7 +48,6 @@
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#include "cc_crypto_ctx.h"
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#include "ssi_sysfs.h"
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#include "hash_defs.h"
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#include "ssi_fips_local.h"
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#include "cc_hw_queue_defs.h"
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#include "ssi_sram_mgr.h"
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@ -14,46 +14,115 @@
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/**************************************************************
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* This file defines the driver FIPS APIs *
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**************************************************************/
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#include <linux/kernel.h>
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#include <linux/fips.h>
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#include <linux/module.h>
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#include "ssi_config.h"
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#include "ssi_driver.h"
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#include "cc_hal.h"
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#include "ssi_fips.h"
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extern int ssi_fips_ext_get_state(enum cc_fips_state_t *p_state);
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extern int ssi_fips_ext_get_error(enum cc_fips_error *p_err);
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static void fips_dsr(unsigned long devarg);
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struct ssi_fips_handle {
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struct tasklet_struct tasklet;
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};
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/* The function called once at driver entry point to check
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* whether TEE FIPS error occurred.
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*/
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static bool cc_get_tee_fips_status(struct ssi_drvdata *drvdata)
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{
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u32 reg;
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void __iomem *cc_base = drvdata->cc_base;
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reg = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GPR_HOST));
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return (reg == (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK));
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}
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/*
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* This function returns the REE FIPS state.
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* It should be called by kernel module.
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* This function should push the FIPS REE library status towards the TEE library
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* by writing the error state to HOST_GPR0 register.
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*/
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int ssi_fips_get_state(enum cc_fips_state_t *p_state)
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void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool status)
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{
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int rc = 0;
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void __iomem *cc_base = drvdata->cc_base;
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int val = CC_FIPS_SYNC_REE_STATUS;
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if (!p_state)
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return -EINVAL;
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val |= (status ? CC_FIPS_SYNC_MODULE_OK : CC_FIPS_SYNC_MODULE_ERROR);
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rc = ssi_fips_ext_get_state(p_state);
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return rc;
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CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), val);
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}
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EXPORT_SYMBOL(ssi_fips_get_state);
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/*
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* This function returns the REE FIPS error.
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* It should be called by kernel module.
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*/
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int ssi_fips_get_error(enum cc_fips_error *p_err)
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void ssi_fips_fini(struct ssi_drvdata *drvdata)
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{
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int rc = 0;
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struct ssi_fips_handle *fips_h = drvdata->fips_handle;
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if (!p_err)
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return -EINVAL;
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if (!fips_h)
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return; /* Not allocated */
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rc = ssi_fips_ext_get_error(p_err);
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/* Kill tasklet */
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tasklet_kill(&fips_h->tasklet);
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return rc;
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kfree(fips_h);
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drvdata->fips_handle = NULL;
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}
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void fips_handler(struct ssi_drvdata *drvdata)
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{
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struct ssi_fips_handle *fips_handle_ptr =
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drvdata->fips_handle;
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tasklet_schedule(&fips_handle_ptr->tasklet);
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}
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static inline void tee_fips_error(void)
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{
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if (fips_enabled)
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panic("ccree: TEE reported cryptographic error in fips mode!\n");
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else
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SSI_LOG_ERR("TEE reported error!\n");
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}
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/* Deferred service handler, run as interrupt-fired tasklet */
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static void fips_dsr(unsigned long devarg)
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{
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struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg;
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void __iomem *cc_base = drvdata->cc_base;
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u32 irq, state, val;
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irq = (drvdata->irq & (SSI_GPR0_IRQ_MASK));
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if (irq) {
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state = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GPR_HOST));
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if (state != (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK))
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tee_fips_error();
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}
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/* after verifing that there is nothing to do,
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* unmask AXI completion interrupt.
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*/
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val = (CC_REG_OFFSET(HOST_RGF, HOST_IMR) & ~irq);
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CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR), val);
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}
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/* The function called once at driver entry point .*/
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int ssi_fips_init(struct ssi_drvdata *p_drvdata)
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{
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struct ssi_fips_handle *fips_h;
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fips_h = kzalloc(sizeof(*fips_h), GFP_KERNEL);
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if (!fips_h)
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return -ENOMEM;
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p_drvdata->fips_handle = fips_h;
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SSI_LOG_DEBUG("Initializing fips tasklet\n");
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tasklet_init(&fips_h->tasklet, fips_dsr, (unsigned long)p_drvdata);
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if (!cc_get_tee_fips_status(p_drvdata))
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tee_fips_error();
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return 0;
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}
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EXPORT_SYMBOL(ssi_fips_get_error);
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@ -17,45 +17,33 @@
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#ifndef __SSI_FIPS_H__
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#define __SSI_FIPS_H__
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/*!
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* @file
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* @brief This file contains FIPS related defintions and APIs.
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*/
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#ifdef CONFIG_CRYPTO_FIPS
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enum cc_fips_state {
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CC_FIPS_STATE_NOT_SUPPORTED = 0,
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CC_FIPS_STATE_SUPPORTED,
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CC_FIPS_STATE_ERROR,
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CC_FIPS_STATE_RESERVE32B = S32_MAX
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enum cc_fips_status {
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CC_FIPS_SYNC_MODULE_OK = 0x0,
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CC_FIPS_SYNC_MODULE_ERROR = 0x1,
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CC_FIPS_SYNC_REE_STATUS = 0x4,
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CC_FIPS_SYNC_TEE_STATUS = 0x8,
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CC_FIPS_SYNC_STATUS_RESERVE32B = S32_MAX
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};
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enum cc_fips_error {
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CC_REE_FIPS_ERROR_OK = 0,
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CC_REE_FIPS_ERROR_GENERAL,
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CC_REE_FIPS_ERROR_FROM_TEE,
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CC_REE_FIPS_ERROR_AES_ECB_PUT,
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CC_REE_FIPS_ERROR_AES_CBC_PUT,
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CC_REE_FIPS_ERROR_AES_OFB_PUT,
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CC_REE_FIPS_ERROR_AES_CTR_PUT,
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CC_REE_FIPS_ERROR_AES_CBC_CTS_PUT,
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CC_REE_FIPS_ERROR_AES_XTS_PUT,
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CC_REE_FIPS_ERROR_AES_CMAC_PUT,
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CC_REE_FIPS_ERROR_AESCCM_PUT,
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CC_REE_FIPS_ERROR_AESGCM_PUT,
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CC_REE_FIPS_ERROR_DES_ECB_PUT,
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CC_REE_FIPS_ERROR_DES_CBC_PUT,
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CC_REE_FIPS_ERROR_SHA1_PUT,
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CC_REE_FIPS_ERROR_SHA256_PUT,
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CC_REE_FIPS_ERROR_SHA512_PUT,
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CC_REE_FIPS_ERROR_HMAC_SHA1_PUT,
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CC_REE_FIPS_ERROR_HMAC_SHA256_PUT,
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CC_REE_FIPS_ERROR_HMAC_SHA512_PUT,
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CC_REE_FIPS_ERROR_ROM_CHECKSUM,
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CC_REE_FIPS_ERROR_RESERVE32B = S32_MAX
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};
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int ssi_fips_init(struct ssi_drvdata *p_drvdata);
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void ssi_fips_fini(struct ssi_drvdata *drvdata);
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void fips_handler(struct ssi_drvdata *drvdata);
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void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool ok);
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int ssi_fips_get_state(enum cc_fips_state *p_state);
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int ssi_fips_get_error(enum cc_fips_error *p_err);
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#else /* CONFIG_CRYPTO_FIPS */
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static inline int ssi_fips_init(struct ssi_drvdata *p_drvdata)
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{
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return 0;
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}
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static inline void ssi_fips_fini(struct ssi_drvdata *drvdata) {}
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void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool ok) {}
|
||||
void fips_handler(struct ssi_drvdata *drvdata) {}
|
||||
|
||||
#endif /* CONFIG_CRYPTO_FIPS */
|
||||
|
||||
#endif /*__SSI_FIPS_H__*/
|
||||
|
||||
|
||||
@ -1,306 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2017 ARM Limited or its affiliates.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The test vectors were taken from:
|
||||
*
|
||||
* * AES
|
||||
* NIST Special Publication 800-38A 2001 Edition
|
||||
* Recommendation for Block Cipher Modes of Operation
|
||||
* http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf
|
||||
* Appendix F: Example Vectors for Modes of Operation of the AES
|
||||
*
|
||||
* * AES CTS
|
||||
* Advanced Encryption Standard (AES) Encryption for Kerberos 5
|
||||
* February 2005
|
||||
* https://tools.ietf.org/html/rfc3962#appendix-B
|
||||
* B. Sample Test Vectors
|
||||
*
|
||||
* * AES XTS
|
||||
* http://csrc.nist.gov/groups/STM/cavp/#08
|
||||
* http://csrc.nist.gov/groups/STM/cavp/documents/aes/XTSTestVectors.zip
|
||||
*
|
||||
* * AES CMAC
|
||||
* http://csrc.nist.gov/groups/STM/cavp/index.html#07
|
||||
* http://csrc.nist.gov/groups/STM/cavp/documents/mac/cmactestvectors.zip
|
||||
*
|
||||
* * AES-CCM
|
||||
* http://csrc.nist.gov/groups/STM/cavp/#07
|
||||
* http://csrc.nist.gov/groups/STM/cavp/documents/mac/ccmtestvectors.zip
|
||||
*
|
||||
* * AES-GCM
|
||||
* http://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip
|
||||
*
|
||||
* * Triple-DES
|
||||
* NIST Special Publication 800-67 January 2012
|
||||
* Recommendation for the Triple Data Encryption Algorithm (TDEA) Block Cipher
|
||||
* http://csrc.nist.gov/publications/nistpubs/800-67-Rev1/SP-800-67-Rev1.pdf
|
||||
* APPENDIX B: EXAMPLE OF TDEA FORWARD AND INVERSE CIPHER OPERATIONS
|
||||
* and
|
||||
* http://csrc.nist.gov/groups/STM/cavp/#01
|
||||
* http://csrc.nist.gov/groups/STM/cavp/documents/des/tdesmct_intermediate.zip
|
||||
*
|
||||
* * HASH
|
||||
* http://csrc.nist.gov/groups/STM/cavp/#03
|
||||
* http://csrc.nist.gov/groups/STM/cavp/documents/shs/shabytetestvectors.zip
|
||||
*
|
||||
* * HMAC
|
||||
* http://csrc.nist.gov/groups/STM/cavp/#07
|
||||
* http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip
|
||||
*/
|
||||
|
||||
/* NIST AES */
|
||||
#define AES_128_BIT_KEY_SIZE 16
|
||||
#define AES_192_BIT_KEY_SIZE 24
|
||||
#define AES_256_BIT_KEY_SIZE 32
|
||||
#define AES_512_BIT_KEY_SIZE 64
|
||||
|
||||
#define NIST_AES_IV_SIZE 16
|
||||
|
||||
#define NIST_AES_128_KEY { 0x2b, 0x7e, 0x15, 0x16, 0x28, 0xae, 0xd2, 0xa6, 0xab, 0xf7, 0x15, 0x88, 0x09, 0xcf, 0x4f, 0x3c }
|
||||
#define NIST_AES_192_KEY { 0x8e, 0x73, 0xb0, 0xf7, 0xda, 0x0e, 0x64, 0x52, 0xc8, 0x10, 0xf3, 0x2b, 0x80, 0x90, 0x79, 0xe5, \
|
||||
0x62, 0xf8, 0xea, 0xd2, 0x52, 0x2c, 0x6b, 0x7b }
|
||||
#define NIST_AES_256_KEY { 0x60, 0x3d, 0xeb, 0x10, 0x15, 0xca, 0x71, 0xbe, 0x2b, 0x73, 0xae, 0xf0, 0x85, 0x7d, 0x77, 0x81, \
|
||||
0x1f, 0x35, 0x2c, 0x07, 0x3b, 0x61, 0x08, 0xd7, 0x2d, 0x98, 0x10, 0xa3, 0x09, 0x14, 0xdf, 0xf4 }
|
||||
#define NIST_AES_VECTOR_SIZE 16
|
||||
#define NIST_AES_PLAIN_DATA { 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a }
|
||||
|
||||
#define NIST_AES_ECB_IV { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
#define NIST_AES_128_ECB_CIPHER { 0x3a, 0xd7, 0x7b, 0xb4, 0x0d, 0x7a, 0x36, 0x60, 0xa8, 0x9e, 0xca, 0xf3, 0x24, 0x66, 0xef, 0x97 }
|
||||
#define NIST_AES_192_ECB_CIPHER { 0xbd, 0x33, 0x4f, 0x1d, 0x6e, 0x45, 0xf2, 0x5f, 0xf7, 0x12, 0xa2, 0x14, 0x57, 0x1f, 0xa5, 0xcc }
|
||||
#define NIST_AES_256_ECB_CIPHER { 0xf3, 0xee, 0xd1, 0xbd, 0xb5, 0xd2, 0xa0, 0x3c, 0x06, 0x4b, 0x5a, 0x7e, 0x3d, 0xb1, 0x81, 0xf8 }
|
||||
|
||||
#define NIST_AES_CBC_IV { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f }
|
||||
#define NIST_AES_128_CBC_CIPHER { 0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d }
|
||||
#define NIST_AES_192_CBC_CIPHER { 0x4f, 0x02, 0x1d, 0xb2, 0x43, 0xbc, 0x63, 0x3d, 0x71, 0x78, 0x18, 0x3a, 0x9f, 0xa0, 0x71, 0xe8 }
|
||||
#define NIST_AES_256_CBC_CIPHER { 0xf5, 0x8c, 0x4c, 0x04, 0xd6, 0xe5, 0xf1, 0xba, 0x77, 0x9e, 0xab, 0xfb, 0x5f, 0x7b, 0xfb, 0xd6 }
|
||||
|
||||
#define NIST_AES_OFB_IV { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f }
|
||||
#define NIST_AES_128_OFB_CIPHER { 0x3b, 0x3f, 0xd9, 0x2e, 0xb7, 0x2d, 0xad, 0x20, 0x33, 0x34, 0x49, 0xf8, 0xe8, 0x3c, 0xfb, 0x4a }
|
||||
#define NIST_AES_192_OFB_CIPHER { 0xcd, 0xc8, 0x0d, 0x6f, 0xdd, 0xf1, 0x8c, 0xab, 0x34, 0xc2, 0x59, 0x09, 0xc9, 0x9a, 0x41, 0x74 }
|
||||
#define NIST_AES_256_OFB_CIPHER { 0xdc, 0x7e, 0x84, 0xbf, 0xda, 0x79, 0x16, 0x4b, 0x7e, 0xcd, 0x84, 0x86, 0x98, 0x5d, 0x38, 0x60 }
|
||||
|
||||
#define NIST_AES_CTR_IV { 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, 0xff }
|
||||
#define NIST_AES_128_CTR_CIPHER { 0x87, 0x4d, 0x61, 0x91, 0xb6, 0x20, 0xe3, 0x26, 0x1b, 0xef, 0x68, 0x64, 0x99, 0x0d, 0xb6, 0xce }
|
||||
#define NIST_AES_192_CTR_CIPHER { 0x1a, 0xbc, 0x93, 0x24, 0x17, 0x52, 0x1c, 0xa2, 0x4f, 0x2b, 0x04, 0x59, 0xfe, 0x7e, 0x6e, 0x0b }
|
||||
#define NIST_AES_256_CTR_CIPHER { 0x60, 0x1e, 0xc3, 0x13, 0x77, 0x57, 0x89, 0xa5, 0xb7, 0xa7, 0xf5, 0x04, 0xbb, 0xf3, 0xd2, 0x28 }
|
||||
|
||||
#define RFC3962_AES_128_KEY { 0x63, 0x68, 0x69, 0x63, 0x6b, 0x65, 0x6e, 0x20, 0x74, 0x65, 0x72, 0x69, 0x79, 0x61, 0x6b, 0x69 }
|
||||
#define RFC3962_AES_VECTOR_SIZE 17
|
||||
#define RFC3962_AES_PLAIN_DATA { 0x49, 0x20, 0x77, 0x6f, 0x75, 0x6c, 0x64, 0x20, 0x6c, 0x69, 0x6b, 0x65, 0x20, 0x74, 0x68, 0x65, 0x20 }
|
||||
#define RFC3962_AES_CBC_CTS_IV { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
#define RFC3962_AES_128_CBC_CTS_CIPHER { 0xc6, 0x35, 0x35, 0x68, 0xf2, 0xbf, 0x8c, 0xb4, 0xd8, 0xa5, 0x80, 0x36, 0x2d, 0xa7, 0xff, 0x7f, 0x97 }
|
||||
|
||||
#define NIST_AES_256_XTS_KEY { 0xa1, 0xb9, 0x0c, 0xba, 0x3f, 0x06, 0xac, 0x35, 0x3b, 0x2c, 0x34, 0x38, 0x76, 0x08, 0x17, 0x62, \
|
||||
0x09, 0x09, 0x23, 0x02, 0x6e, 0x91, 0x77, 0x18, 0x15, 0xf2, 0x9d, 0xab, 0x01, 0x93, 0x2f, 0x2f }
|
||||
#define NIST_AES_256_XTS_IV { 0x4f, 0xae, 0xf7, 0x11, 0x7c, 0xda, 0x59, 0xc6, 0x6e, 0x4b, 0x92, 0x01, 0x3e, 0x76, 0x8a, 0xd5 }
|
||||
#define NIST_AES_256_XTS_VECTOR_SIZE 16
|
||||
#define NIST_AES_256_XTS_PLAIN { 0xeb, 0xab, 0xce, 0x95, 0xb1, 0x4d, 0x3c, 0x8d, 0x6f, 0xb3, 0x50, 0x39, 0x07, 0x90, 0x31, 0x1c }
|
||||
#define NIST_AES_256_XTS_CIPHER { 0x77, 0x8a, 0xe8, 0xb4, 0x3c, 0xb9, 0x8d, 0x5a, 0x82, 0x50, 0x81, 0xd5, 0xbe, 0x47, 0x1c, 0x63 }
|
||||
|
||||
#define NIST_AES_512_XTS_KEY { 0x1e, 0xa6, 0x61, 0xc5, 0x8d, 0x94, 0x3a, 0x0e, 0x48, 0x01, 0xe4, 0x2f, 0x4b, 0x09, 0x47, 0x14, \
|
||||
0x9e, 0x7f, 0x9f, 0x8e, 0x3e, 0x68, 0xd0, 0xc7, 0x50, 0x52, 0x10, 0xbd, 0x31, 0x1a, 0x0e, 0x7c, \
|
||||
0xd6, 0xe1, 0x3f, 0xfd, 0xf2, 0x41, 0x8d, 0x8d, 0x19, 0x11, 0xc0, 0x04, 0xcd, 0xa5, 0x8d, 0xa3, \
|
||||
0xd6, 0x19, 0xb7, 0xe2, 0xb9, 0x14, 0x1e, 0x58, 0x31, 0x8e, 0xea, 0x39, 0x2c, 0xf4, 0x1b, 0x08 }
|
||||
#define NIST_AES_512_XTS_IV { 0xad, 0xf8, 0xd9, 0x26, 0x27, 0x46, 0x4a, 0xd2, 0xf0, 0x42, 0x8e, 0x84, 0xa9, 0xf8, 0x75, 0x64, }
|
||||
#define NIST_AES_512_XTS_VECTOR_SIZE 32
|
||||
#define NIST_AES_512_XTS_PLAIN { 0x2e, 0xed, 0xea, 0x52, 0xcd, 0x82, 0x15, 0xe1, 0xac, 0xc6, 0x47, 0xe8, 0x10, 0xbb, 0xc3, 0x64, \
|
||||
0x2e, 0x87, 0x28, 0x7f, 0x8d, 0x2e, 0x57, 0xe3, 0x6c, 0x0a, 0x24, 0xfb, 0xc1, 0x2a, 0x20, 0x2e }
|
||||
#define NIST_AES_512_XTS_CIPHER { 0xcb, 0xaa, 0xd0, 0xe2, 0xf6, 0xce, 0xa3, 0xf5, 0x0b, 0x37, 0xf9, 0x34, 0xd4, 0x6a, 0x9b, 0x13, \
|
||||
0x0b, 0x9d, 0x54, 0xf0, 0x7e, 0x34, 0xf3, 0x6a, 0xf7, 0x93, 0xe8, 0x6f, 0x73, 0xc6, 0xd7, 0xdb }
|
||||
|
||||
/* NIST AES-CMAC */
|
||||
#define NIST_AES_128_CMAC_KEY { 0x67, 0x08, 0xc9, 0x88, 0x7b, 0x84, 0x70, 0x84, 0xf1, 0x23, 0xd3, 0xdd, 0x9c, 0x3a, 0x81, 0x36 }
|
||||
#define NIST_AES_128_CMAC_PLAIN_DATA { 0xa8, 0xde, 0x55, 0x17, 0x0c, 0x6d, 0xc0, 0xd8, 0x0d, 0xe3, 0x2f, 0x50, 0x8b, 0xf4, 0x9b, 0x70 }
|
||||
#define NIST_AES_128_CMAC_MAC { 0xcf, 0xef, 0x9b, 0x78, 0x39, 0x84, 0x1f, 0xdb, 0xcc, 0xbb, 0x6c, 0x2c, 0xf2, 0x38, 0xf7 }
|
||||
#define NIST_AES_128_CMAC_VECTOR_SIZE 16
|
||||
#define NIST_AES_128_CMAC_OUTPUT_SIZE 15
|
||||
|
||||
#define NIST_AES_192_CMAC_KEY { 0x20, 0x51, 0xaf, 0x34, 0x76, 0x2e, 0xbe, 0x55, 0x6f, 0x72, 0xa5, 0xc6, 0xed, 0xc7, 0x77, 0x1e, \
|
||||
0xb9, 0x24, 0x5f, 0xad, 0x76, 0xf0, 0x34, 0xbe }
|
||||
#define NIST_AES_192_CMAC_PLAIN_DATA { 0xae, 0x8e, 0x93, 0xc9, 0xc9, 0x91, 0xcf, 0x89, 0x6a, 0x49, 0x1a, 0x89, 0x07, 0xdf, 0x4e, 0x4b, \
|
||||
0xe5, 0x18, 0x6a, 0xe4, 0x96, 0xcd, 0x34, 0x0d, 0xc1, 0x9b, 0x23, 0x78, 0x21, 0xdb, 0x7b, 0x60 }
|
||||
#define NIST_AES_192_CMAC_MAC { 0x74, 0xf7, 0x46, 0x08, 0xc0, 0x4f, 0x0f, 0x4e, 0x47, 0xfa, 0x64, 0x04, 0x33, 0xb6, 0xe6, 0xfb }
|
||||
#define NIST_AES_192_CMAC_VECTOR_SIZE 32
|
||||
#define NIST_AES_192_CMAC_OUTPUT_SIZE 16
|
||||
|
||||
#define NIST_AES_256_CMAC_KEY { 0x3a, 0x75, 0xa9, 0xd2, 0xbd, 0xb8, 0xc8, 0x04, 0xba, 0x4a, 0xb4, 0x98, 0x35, 0x73, 0xa6, 0xb2, \
|
||||
0x53, 0x16, 0x0d, 0xd9, 0x0f, 0x8e, 0xdd, 0xfb, 0x2f, 0xdc, 0x2a, 0xb1, 0x76, 0x04, 0xf5, 0xc5 }
|
||||
#define NIST_AES_256_CMAC_PLAIN_DATA { 0x42, 0xf3, 0x5d, 0x5a, 0xa5, 0x33, 0xa7, 0xa0, 0xa5, 0xf7, 0x4e, 0x14, 0x4f, 0x2a, 0x5f, 0x20 }
|
||||
#define NIST_AES_256_CMAC_MAC { 0xf1, 0x53, 0x2f, 0x87, 0x32, 0xd9, 0xf5, 0x90, 0x30, 0x07 }
|
||||
#define NIST_AES_256_CMAC_VECTOR_SIZE 16
|
||||
#define NIST_AES_256_CMAC_OUTPUT_SIZE 10
|
||||
|
||||
/* NIST TDES */
|
||||
#define TDES_NUM_OF_KEYS 3
|
||||
#define NIST_TDES_VECTOR_SIZE 8
|
||||
#define NIST_TDES_IV_SIZE 8
|
||||
|
||||
#define NIST_TDES_ECB_IV { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }
|
||||
|
||||
#define NIST_TDES_ECB3_KEY { 0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, \
|
||||
0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0x01, \
|
||||
0x45, 0x67, 0x89, 0xab, 0xcd, 0xef, 0x01, 0x23 }
|
||||
#define NIST_TDES_ECB3_PLAIN_DATA { 0x54, 0x68, 0x65, 0x20, 0x71, 0x75, 0x66, 0x63 }
|
||||
#define NIST_TDES_ECB3_CIPHER { 0xa8, 0x26, 0xfd, 0x8c, 0xe5, 0x3b, 0x85, 0x5f }
|
||||
|
||||
#define NIST_TDES_CBC3_IV { 0xf8, 0xee, 0xe1, 0x35, 0x9c, 0x6e, 0x54, 0x40 }
|
||||
#define NIST_TDES_CBC3_KEY { 0xe9, 0xda, 0x37, 0xf8, 0xdc, 0x97, 0x6d, 0x5b, \
|
||||
0xb6, 0x8c, 0x04, 0xe3, 0xec, 0x98, 0x20, 0x15, \
|
||||
0xf4, 0x0e, 0x08, 0xb5, 0x97, 0x29, 0xf2, 0x8f }
|
||||
#define NIST_TDES_CBC3_PLAIN_DATA { 0x3b, 0xb7, 0xa7, 0xdb, 0xa3, 0xd5, 0x92, 0x91 }
|
||||
#define NIST_TDES_CBC3_CIPHER { 0x5b, 0x84, 0x24, 0xd2, 0x39, 0x3e, 0x55, 0xa2 }
|
||||
|
||||
/* NIST AES-CCM */
|
||||
#define NIST_AESCCM_128_BIT_KEY_SIZE 16
|
||||
#define NIST_AESCCM_192_BIT_KEY_SIZE 24
|
||||
#define NIST_AESCCM_256_BIT_KEY_SIZE 32
|
||||
|
||||
#define NIST_AESCCM_B0_VAL 0x79 /* L'[0:2]=1 , M'[3-5]=7 , Adata[6]=1, reserved[7]=0 */
|
||||
#define NIST_AESCCM_NONCE_SIZE 13
|
||||
#define NIST_AESCCM_IV_SIZE 16
|
||||
#define NIST_AESCCM_ADATA_SIZE 32
|
||||
#define NIST_AESCCM_TEXT_SIZE 16
|
||||
#define NIST_AESCCM_TAG_SIZE 16
|
||||
|
||||
#define NIST_AESCCM_128_KEY { 0x70, 0x01, 0x0e, 0xd9, 0x0e, 0x61, 0x86, 0xec, 0xad, 0x41, 0xf0, 0xd3, 0xc7, 0xc4, 0x2f, 0xf8 }
|
||||
#define NIST_AESCCM_128_NONCE { 0xa5, 0xf4, 0xf4, 0x98, 0x6e, 0x98, 0x47, 0x29, 0x65, 0xf5, 0xab, 0xcc, 0x4b }
|
||||
#define NIST_AESCCM_128_ADATA { 0x3f, 0xec, 0x0e, 0x5c, 0xc2, 0x4d, 0x67, 0x13, 0x94, 0x37, 0xcb, 0xc8, 0x11, 0x24, 0x14, 0xfc, \
|
||||
0x8d, 0xac, 0xcd, 0x1a, 0x94, 0xb4, 0x9a, 0x4c, 0x76, 0xe2, 0xd3, 0x93, 0x03, 0x54, 0x73, 0x17 }
|
||||
#define NIST_AESCCM_128_PLAIN_TEXT { 0xbe, 0x32, 0x2f, 0x58, 0xef, 0xa7, 0xf8, 0xc6, 0x8a, 0x63, 0x5e, 0x0b, 0x9c, 0xce, 0x77, 0xf2 }
|
||||
#define NIST_AESCCM_128_CIPHER { 0x8e, 0x44, 0x25, 0xae, 0x57, 0x39, 0x74, 0xf0, 0xf0, 0x69, 0x3a, 0x18, 0x8b, 0x52, 0x58, 0x12 }
|
||||
#define NIST_AESCCM_128_MAC { 0xee, 0xf0, 0x8e, 0x3f, 0xb1, 0x5f, 0x42, 0x27, 0xe0, 0xd9, 0x89, 0xa4, 0xd5, 0x87, 0xa8, 0xcf }
|
||||
|
||||
#define NIST_AESCCM_192_KEY { 0x68, 0x73, 0xf1, 0xc6, 0xc3, 0x09, 0x75, 0xaf, 0xf6, 0xf0, 0x84, 0x70, 0x26, 0x43, 0x21, 0x13, \
|
||||
0x0a, 0x6e, 0x59, 0x84, 0xad, 0xe3, 0x24, 0xe9 }
|
||||
#define NIST_AESCCM_192_NONCE { 0x7c, 0x4d, 0x2f, 0x7c, 0xec, 0x04, 0x36, 0x1f, 0x18, 0x7f, 0x07, 0x26, 0xd5 }
|
||||
#define NIST_AESCCM_192_ADATA { 0x77, 0x74, 0x3b, 0x5d, 0x83, 0xa0, 0x0d, 0x2c, 0x8d, 0x5f, 0x7e, 0x10, 0x78, 0x15, 0x31, 0xb4, \
|
||||
0x96, 0xe0, 0x9f, 0x3b, 0xc9, 0x29, 0x5d, 0x7a, 0xe9, 0x79, 0x9e, 0x64, 0x66, 0x8e, 0xf8, 0xc5 }
|
||||
#define NIST_AESCCM_192_PLAIN_TEXT { 0x50, 0x51, 0xa0, 0xb0, 0xb6, 0x76, 0x6c, 0xd6, 0xea, 0x29, 0xa6, 0x72, 0x76, 0x9d, 0x40, 0xfe }
|
||||
#define NIST_AESCCM_192_CIPHER { 0x0c, 0xe5, 0xac, 0x8d, 0x6b, 0x25, 0x6f, 0xb7, 0x58, 0x0b, 0xf6, 0xac, 0xc7, 0x64, 0x26, 0xaf }
|
||||
#define NIST_AESCCM_192_MAC { 0x40, 0xbc, 0xe5, 0x8f, 0xd4, 0xcd, 0x65, 0x48, 0xdf, 0x90, 0xa0, 0x33, 0x7c, 0x84, 0x20, 0x04 }
|
||||
|
||||
#define NIST_AESCCM_256_KEY { 0xee, 0x8c, 0xe1, 0x87, 0x16, 0x97, 0x79, 0xd1, 0x3e, 0x44, 0x3d, 0x64, 0x28, 0xe3, 0x8b, 0x38, \
|
||||
0xb5, 0x5d, 0xfb, 0x90, 0xf0, 0x22, 0x8a, 0x8a, 0x4e, 0x62, 0xf8, 0xf5, 0x35, 0x80, 0x6e, 0x62 }
|
||||
#define NIST_AESCCM_256_NONCE { 0x12, 0x16, 0x42, 0xc4, 0x21, 0x8b, 0x39, 0x1c, 0x98, 0xe6, 0x26, 0x9c, 0x8a }
|
||||
#define NIST_AESCCM_256_ADATA { 0x71, 0x8d, 0x13, 0xe4, 0x75, 0x22, 0xac, 0x4c, 0xdf, 0x3f, 0x82, 0x80, 0x63, 0x98, 0x0b, 0x6d, \
|
||||
0x45, 0x2f, 0xcd, 0xcd, 0x6e, 0x1a, 0x19, 0x04, 0xbf, 0x87, 0xf5, 0x48, 0xa5, 0xfd, 0x5a, 0x05 }
|
||||
#define NIST_AESCCM_256_PLAIN_TEXT { 0xd1, 0x5f, 0x98, 0xf2, 0xc6, 0xd6, 0x70, 0xf5, 0x5c, 0x78, 0xa0, 0x66, 0x48, 0x33, 0x2b, 0xc9 }
|
||||
#define NIST_AESCCM_256_CIPHER { 0xcc, 0x17, 0xbf, 0x87, 0x94, 0xc8, 0x43, 0x45, 0x7d, 0x89, 0x93, 0x91, 0x89, 0x8e, 0xd2, 0x2a }
|
||||
#define NIST_AESCCM_256_MAC { 0x6f, 0x9d, 0x28, 0xfc, 0xb6, 0x42, 0x34, 0xe1, 0xcd, 0x79, 0x3c, 0x41, 0x44, 0xf1, 0xda, 0x50 }
|
||||
|
||||
/* NIST AES-GCM */
|
||||
#define NIST_AESGCM_128_BIT_KEY_SIZE 16
|
||||
#define NIST_AESGCM_192_BIT_KEY_SIZE 24
|
||||
#define NIST_AESGCM_256_BIT_KEY_SIZE 32
|
||||
|
||||
#define NIST_AESGCM_IV_SIZE 12
|
||||
#define NIST_AESGCM_ADATA_SIZE 16
|
||||
#define NIST_AESGCM_TEXT_SIZE 16
|
||||
#define NIST_AESGCM_TAG_SIZE 16
|
||||
|
||||
#define NIST_AESGCM_128_KEY { 0x81, 0x6e, 0x39, 0x07, 0x04, 0x10, 0xcf, 0x21, 0x84, 0x90, 0x4d, 0xa0, 0x3e, 0xa5, 0x07, 0x5a }
|
||||
#define NIST_AESGCM_128_IV { 0x32, 0xc3, 0x67, 0xa3, 0x36, 0x26, 0x13, 0xb2, 0x7f, 0xc3, 0xe6, 0x7e }
|
||||
#define NIST_AESGCM_128_ADATA { 0xf2, 0xa3, 0x07, 0x28, 0xed, 0x87, 0x4e, 0xe0, 0x29, 0x83, 0xc2, 0x94, 0x43, 0x5d, 0x3c, 0x16 }
|
||||
#define NIST_AESGCM_128_PLAIN_TEXT { 0xec, 0xaf, 0xe9, 0x6c, 0x67, 0xa1, 0x64, 0x67, 0x44, 0xf1, 0xc8, 0x91, 0xf5, 0xe6, 0x94, 0x27 }
|
||||
#define NIST_AESGCM_128_CIPHER { 0x55, 0x2e, 0xbe, 0x01, 0x2e, 0x7b, 0xcf, 0x90, 0xfc, 0xef, 0x71, 0x2f, 0x83, 0x44, 0xe8, 0xf1 }
|
||||
#define NIST_AESGCM_128_MAC { 0xec, 0xaa, 0xe9, 0xfc, 0x68, 0x27, 0x6a, 0x45, 0xab, 0x0c, 0xa3, 0xcb, 0x9d, 0xd9, 0x53, 0x9f }
|
||||
|
||||
#define NIST_AESGCM_192_KEY { 0x0c, 0x44, 0xd6, 0xc9, 0x28, 0xee, 0x11, 0x2c, 0xe6, 0x65, 0xfe, 0x54, 0x7e, 0xbd, 0x38, 0x72, \
|
||||
0x98, 0xa9, 0x54, 0xb4, 0x62, 0xf6, 0x95, 0xd8 }
|
||||
#define NIST_AESGCM_192_IV { 0x18, 0xb8, 0xf3, 0x20, 0xfe, 0xf4, 0xae, 0x8c, 0xcb, 0xe8, 0xf9, 0x52 }
|
||||
#define NIST_AESGCM_192_ADATA { 0x73, 0x41, 0xd4, 0x3f, 0x98, 0xcf, 0x38, 0x82, 0x21, 0x18, 0x09, 0x41, 0x97, 0x03, 0x76, 0xe8 }
|
||||
#define NIST_AESGCM_192_PLAIN_TEXT { 0x96, 0xad, 0x07, 0xf9, 0xb6, 0x28, 0xb6, 0x52, 0xcf, 0x86, 0xcb, 0x73, 0x17, 0x88, 0x6f, 0x51 }
|
||||
#define NIST_AESGCM_192_CIPHER { 0xa6, 0x64, 0x07, 0x81, 0x33, 0x40, 0x5e, 0xb9, 0x09, 0x4d, 0x36, 0xf7, 0xe0, 0x70, 0x19, 0x1f }
|
||||
#define NIST_AESGCM_192_MAC { 0xe8, 0xf9, 0xc3, 0x17, 0x84, 0x7c, 0xe3, 0xf3, 0xc2, 0x39, 0x94, 0xa4, 0x02, 0xf0, 0x65, 0x81 }
|
||||
|
||||
#define NIST_AESGCM_256_KEY { 0x54, 0xe3, 0x52, 0xea, 0x1d, 0x84, 0xbf, 0xe6, 0x4a, 0x10, 0x11, 0x09, 0x61, 0x11, 0xfb, 0xe7, \
|
||||
0x66, 0x8a, 0xd2, 0x20, 0x3d, 0x90, 0x2a, 0x01, 0x45, 0x8c, 0x3b, 0xbd, 0x85, 0xbf, 0xce, 0x14 }
|
||||
#define NIST_AESGCM_256_IV { 0xdf, 0x7c, 0x3b, 0xca, 0x00, 0x39, 0x6d, 0x0c, 0x01, 0x84, 0x95, 0xd9 }
|
||||
#define NIST_AESGCM_256_ADATA { 0x7e, 0x96, 0x8d, 0x71, 0xb5, 0x0c, 0x1f, 0x11, 0xfd, 0x00, 0x1f, 0x3f, 0xef, 0x49, 0xd0, 0x45 }
|
||||
#define NIST_AESGCM_256_PLAIN_TEXT { 0x85, 0xfc, 0x3d, 0xfa, 0xd9, 0xb5, 0xa8, 0xd3, 0x25, 0x8e, 0x4f, 0xc4, 0x45, 0x71, 0xbd, 0x3b }
|
||||
#define NIST_AESGCM_256_CIPHER { 0x42, 0x6e, 0x0e, 0xfc, 0x69, 0x3b, 0x7b, 0xe1, 0xf3, 0x01, 0x8d, 0xb7, 0xdd, 0xbb, 0x7e, 0x4d }
|
||||
#define NIST_AESGCM_256_MAC { 0xee, 0x82, 0x57, 0x79, 0x5b, 0xe6, 0xa1, 0x16, 0x4d, 0x7e, 0x1d, 0x2d, 0x6c, 0xac, 0x77, 0xa7 }
|
||||
|
||||
/* NIST HASH */
|
||||
#define NIST_SHA_MSG_SIZE 16
|
||||
|
||||
#define NIST_SHA_1_MSG { 0x35, 0x52, 0x69, 0x4c, 0xdf, 0x66, 0x3f, 0xd9, 0x4b, 0x22, 0x47, 0x47, 0xac, 0x40, 0x6a, 0xaf }
|
||||
#define NIST_SHA_1_MD { 0xa1, 0x50, 0xde, 0x92, 0x74, 0x54, 0x20, 0x2d, 0x94, 0xe6, 0x56, 0xde, 0x4c, 0x7c, 0x0c, 0xa6, \
|
||||
0x91, 0xde, 0x95, 0x5d }
|
||||
|
||||
#define NIST_SHA_256_MSG { 0x0a, 0x27, 0x84, 0x7c, 0xdc, 0x98, 0xbd, 0x6f, 0x62, 0x22, 0x0b, 0x04, 0x6e, 0xdd, 0x76, 0x2b }
|
||||
#define NIST_SHA_256_MD { 0x80, 0xc2, 0x5e, 0xc1, 0x60, 0x05, 0x87, 0xe7, 0xf2, 0x8b, 0x18, 0xb1, 0xb1, 0x8e, 0x3c, 0xdc, \
|
||||
0x89, 0x92, 0x8e, 0x39, 0xca, 0xb3, 0xbc, 0x25, 0xe4, 0xd4, 0xa4, 0xc1, 0x39, 0xbc, 0xed, 0xc4 }
|
||||
|
||||
#define NIST_SHA_512_MSG { 0xcd, 0x67, 0xbd, 0x40, 0x54, 0xaa, 0xa3, 0xba, 0xa0, 0xdb, 0x17, 0x8c, 0xe2, 0x32, 0xfd, 0x5a }
|
||||
#define NIST_SHA_512_MD { 0x0d, 0x85, 0x21, 0xf8, 0xf2, 0xf3, 0x90, 0x03, 0x32, 0xd1, 0xa1, 0xa5, 0x5c, 0x60, 0xba, 0x81, \
|
||||
0xd0, 0x4d, 0x28, 0xdf, 0xe8, 0xc5, 0x04, 0xb6, 0x32, 0x8a, 0xe7, 0x87, 0x92, 0x5f, 0xe0, 0x18, \
|
||||
0x8f, 0x2b, 0xa9, 0x1c, 0x3a, 0x9f, 0x0c, 0x16, 0x53, 0xc4, 0xbf, 0x0a, 0xda, 0x35, 0x64, 0x55, \
|
||||
0xea, 0x36, 0xfd, 0x31, 0xf8, 0xe7, 0x3e, 0x39, 0x51, 0xca, 0xd4, 0xeb, 0xba, 0x8c, 0x6e, 0x04 }
|
||||
|
||||
/* NIST HMAC */
|
||||
#define NIST_HMAC_MSG_SIZE 128
|
||||
|
||||
#define NIST_HMAC_SHA1_KEY_SIZE 10
|
||||
#define NIST_HMAC_SHA1_KEY { 0x59, 0x78, 0x59, 0x28, 0xd7, 0x25, 0x16, 0xe3, 0x12, 0x72 }
|
||||
#define NIST_HMAC_SHA1_MSG { 0xa3, 0xce, 0x88, 0x99, 0xdf, 0x10, 0x22, 0xe8, 0xd2, 0xd5, 0x39, 0xb4, 0x7b, 0xf0, 0xe3, 0x09, \
|
||||
0xc6, 0x6f, 0x84, 0x09, 0x5e, 0x21, 0x43, 0x8e, 0xc3, 0x55, 0xbf, 0x11, 0x9c, 0xe5, 0xfd, 0xcb, \
|
||||
0x4e, 0x73, 0xa6, 0x19, 0xcd, 0xf3, 0x6f, 0x25, 0xb3, 0x69, 0xd8, 0xc3, 0x8f, 0xf4, 0x19, 0x99, \
|
||||
0x7f, 0x0c, 0x59, 0x83, 0x01, 0x08, 0x22, 0x36, 0x06, 0xe3, 0x12, 0x23, 0x48, 0x3f, 0xd3, 0x9e, \
|
||||
0xde, 0xaa, 0x4d, 0x3f, 0x0d, 0x21, 0x19, 0x88, 0x62, 0xd2, 0x39, 0xc9, 0xfd, 0x26, 0x07, 0x41, \
|
||||
0x30, 0xff, 0x6c, 0x86, 0x49, 0x3f, 0x52, 0x27, 0xab, 0x89, 0x5c, 0x8f, 0x24, 0x4b, 0xd4, 0x2c, \
|
||||
0x7a, 0xfc, 0xe5, 0xd1, 0x47, 0xa2, 0x0a, 0x59, 0x07, 0x98, 0xc6, 0x8e, 0x70, 0x8e, 0x96, 0x49, \
|
||||
0x02, 0xd1, 0x24, 0xda, 0xde, 0xcd, 0xbd, 0xa9, 0xdb, 0xd0, 0x05, 0x1e, 0xd7, 0x10, 0xe9, 0xbf }
|
||||
#define NIST_HMAC_SHA1_MD { 0x3c, 0x81, 0x62, 0x58, 0x9a, 0xaf, 0xae, 0xe0, 0x24, 0xfc, 0x9a, 0x5c, 0xa5, 0x0d, 0xd2, 0x33, \
|
||||
0x6f, 0xe3, 0xeb, 0x28 }
|
||||
|
||||
#define NIST_HMAC_SHA256_KEY_SIZE 40
|
||||
#define NIST_HMAC_SHA256_KEY { 0x97, 0x79, 0xd9, 0x12, 0x06, 0x42, 0x79, 0x7f, 0x17, 0x47, 0x02, 0x5d, 0x5b, 0x22, 0xb7, 0xac, \
|
||||
0x60, 0x7c, 0xab, 0x08, 0xe1, 0x75, 0x8f, 0x2f, 0x3a, 0x46, 0xc8, 0xbe, 0x1e, 0x25, 0xc5, 0x3b, \
|
||||
0x8c, 0x6a, 0x8f, 0x58, 0xff, 0xef, 0xa1, 0x76 }
|
||||
#define NIST_HMAC_SHA256_MSG { 0xb1, 0x68, 0x9c, 0x25, 0x91, 0xea, 0xf3, 0xc9, 0xe6, 0x60, 0x70, 0xf8, 0xa7, 0x79, 0x54, 0xff, \
|
||||
0xb8, 0x17, 0x49, 0xf1, 0xb0, 0x03, 0x46, 0xf9, 0xdf, 0xe0, 0xb2, 0xee, 0x90, 0x5d, 0xcc, 0x28, \
|
||||
0x8b, 0xaf, 0x4a, 0x92, 0xde, 0x3f, 0x40, 0x01, 0xdd, 0x9f, 0x44, 0xc4, 0x68, 0xc3, 0xd0, 0x7d, \
|
||||
0x6c, 0x6e, 0xe8, 0x2f, 0xac, 0xea, 0xfc, 0x97, 0xc2, 0xfc, 0x0f, 0xc0, 0x60, 0x17, 0x19, 0xd2, \
|
||||
0xdc, 0xd0, 0xaa, 0x2a, 0xec, 0x92, 0xd1, 0xb0, 0xae, 0x93, 0x3c, 0x65, 0xeb, 0x06, 0xa0, 0x3c, \
|
||||
0x9c, 0x93, 0x5c, 0x2b, 0xad, 0x04, 0x59, 0x81, 0x02, 0x41, 0x34, 0x7a, 0xb8, 0x7e, 0x9f, 0x11, \
|
||||
0xad, 0xb3, 0x04, 0x15, 0x42, 0x4c, 0x6c, 0x7f, 0x5f, 0x22, 0xa0, 0x03, 0xb8, 0xab, 0x8d, 0xe5, \
|
||||
0x4f, 0x6d, 0xed, 0x0e, 0x3a, 0xb9, 0x24, 0x5f, 0xa7, 0x95, 0x68, 0x45, 0x1d, 0xfa, 0x25, 0x8e }
|
||||
#define NIST_HMAC_SHA256_MD { 0x76, 0x9f, 0x00, 0xd3, 0xe6, 0xa6, 0xcc, 0x1f, 0xb4, 0x26, 0xa1, 0x4a, 0x4f, 0x76, 0xc6, 0x46, \
|
||||
0x2e, 0x61, 0x49, 0x72, 0x6e, 0x0d, 0xee, 0x0e, 0xc0, 0xcf, 0x97, 0xa1, 0x66, 0x05, 0xac, 0x8b }
|
||||
|
||||
#define NIST_HMAC_SHA512_KEY_SIZE 100
|
||||
#define NIST_HMAC_SHA512_KEY { 0x57, 0xc2, 0xeb, 0x67, 0x7b, 0x50, 0x93, 0xb9, 0xe8, 0x29, 0xea, 0x4b, 0xab, 0xb5, 0x0b, 0xde, \
|
||||
0x55, 0xd0, 0xad, 0x59, 0xfe, 0xc3, 0x4a, 0x61, 0x89, 0x73, 0x80, 0x2b, 0x2a, 0xd9, 0xb7, 0x8e, \
|
||||
0x26, 0xb2, 0x04, 0x5d, 0xda, 0x78, 0x4d, 0xf3, 0xff, 0x90, 0xae, 0x0f, 0x2c, 0xc5, 0x1c, 0xe3, \
|
||||
0x9c, 0xf5, 0x48, 0x67, 0x32, 0x0a, 0xc6, 0xf3, 0xba, 0x2c, 0x6f, 0x0d, 0x72, 0x36, 0x04, 0x80, \
|
||||
0xc9, 0x66, 0x14, 0xae, 0x66, 0x58, 0x1f, 0x26, 0x6c, 0x35, 0xfb, 0x79, 0xfd, 0x28, 0x77, 0x4a, \
|
||||
0xfd, 0x11, 0x3f, 0xa5, 0x18, 0x7e, 0xff, 0x92, 0x06, 0xd7, 0xcb, 0xe9, 0x0d, 0xd8, 0xbf, 0x67, \
|
||||
0xc8, 0x44, 0xe2, 0x02 }
|
||||
#define NIST_HMAC_SHA512_MSG { 0x24, 0x23, 0xdf, 0xf4, 0x8b, 0x31, 0x2b, 0xe8, 0x64, 0xcb, 0x34, 0x90, 0x64, 0x1f, 0x79, 0x3d, \
|
||||
0x2b, 0x9f, 0xb6, 0x8a, 0x77, 0x63, 0xb8, 0xe2, 0x98, 0xc8, 0x6f, 0x42, 0x24, 0x5e, 0x45, 0x40, \
|
||||
0xeb, 0x01, 0xae, 0x4d, 0x2d, 0x45, 0x00, 0x37, 0x0b, 0x18, 0x86, 0xf2, 0x3c, 0xa2, 0xcf, 0x97, \
|
||||
0x01, 0x70, 0x4c, 0xad, 0x5b, 0xd2, 0x1b, 0xa8, 0x7b, 0x81, 0x1d, 0xaf, 0x7a, 0x85, 0x4e, 0xa2, \
|
||||
0x4a, 0x56, 0x56, 0x5c, 0xed, 0x42, 0x5b, 0x35, 0xe4, 0x0e, 0x1a, 0xcb, 0xeb, 0xe0, 0x36, 0x03, \
|
||||
0xe3, 0x5d, 0xcf, 0x4a, 0x10, 0x0e, 0x57, 0x21, 0x84, 0x08, 0xa1, 0xd8, 0xdb, 0xcc, 0x3b, 0x99, \
|
||||
0x29, 0x6c, 0xfe, 0xa9, 0x31, 0xef, 0xe3, 0xeb, 0xd8, 0xf7, 0x19, 0xa6, 0xd9, 0xa1, 0x54, 0x87, \
|
||||
0xb9, 0xad, 0x67, 0xea, 0xfe, 0xdf, 0x15, 0x55, 0x9c, 0xa4, 0x24, 0x45, 0xb0, 0xf9, 0xb4, 0x2e }
|
||||
#define NIST_HMAC_SHA512_MD { 0x33, 0xc5, 0x11, 0xe9, 0xbc, 0x23, 0x07, 0xc6, 0x27, 0x58, 0xdf, 0x61, 0x12, 0x5a, 0x98, 0x0e, \
|
||||
0xe6, 0x4c, 0xef, 0xeb, 0xd9, 0x09, 0x31, 0xcb, 0x91, 0xc1, 0x37, 0x42, 0xd4, 0x71, 0x4c, 0x06, \
|
||||
0xde, 0x40, 0x03, 0xfa, 0xf3, 0xc4, 0x1c, 0x06, 0xae, 0xfc, 0x63, 0x8a, 0xd4, 0x7b, 0x21, 0x90, \
|
||||
0x6e, 0x6b, 0x10, 0x48, 0x16, 0xb7, 0x2d, 0xe6, 0x26, 0x9e, 0x04, 0x5a, 0x1f, 0x44, 0x29, 0xd4 }
|
||||
|
||||
@ -1,92 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2017 ARM Limited or its affiliates.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**************************************************************
|
||||
* This file defines the driver FIPS functions that should be
|
||||
* implemented by the driver user. Current implementation is sample code only.
|
||||
***************************************************************/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include "ssi_fips_local.h"
|
||||
#include "ssi_driver.h"
|
||||
|
||||
static bool tee_error;
|
||||
module_param(tee_error, bool, 0644);
|
||||
MODULE_PARM_DESC(tee_error, "Simulate TEE library failure flag: 0 - no error (default), 1 - TEE error occured ");
|
||||
|
||||
static enum cc_fips_state_t fips_state = CC_FIPS_STATE_NOT_SUPPORTED;
|
||||
static enum cc_fips_error fips_error = CC_REE_FIPS_ERROR_OK;
|
||||
|
||||
/*
|
||||
* This function returns the FIPS REE state.
|
||||
* The function should be implemented by the driver user, depends on where
|
||||
* the state value is stored.
|
||||
* The reference code uses global variable.
|
||||
*/
|
||||
int ssi_fips_ext_get_state(enum cc_fips_state_t *p_state)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
if (!p_state)
|
||||
return -EINVAL;
|
||||
|
||||
*p_state = fips_state;
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function returns the FIPS REE error.
|
||||
* The function should be implemented by the driver user, depends on where
|
||||
* the error value is stored.
|
||||
* The reference code uses global variable.
|
||||
*/
|
||||
int ssi_fips_ext_get_error(enum cc_fips_error *p_err)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
if (!p_err)
|
||||
return -EINVAL;
|
||||
|
||||
*p_err = fips_error;
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function sets the FIPS REE state.
|
||||
* The function should be implemented by the driver user, depends on where
|
||||
* the state value is stored.
|
||||
* The reference code uses global variable.
|
||||
*/
|
||||
int ssi_fips_ext_set_state(enum cc_fips_state_t state)
|
||||
{
|
||||
fips_state = state;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function sets the FIPS REE error.
|
||||
* The function should be implemented by the driver user, depends on where
|
||||
* the error value is stored.
|
||||
* The reference code uses global variable.
|
||||
*/
|
||||
int ssi_fips_ext_set_error(enum cc_fips_error err)
|
||||
{
|
||||
fips_error = err;
|
||||
return 0;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,357 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2017 ARM Limited or its affiliates.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**************************************************************
|
||||
* This file defines the driver FIPS internal function, used by the driver itself.
|
||||
***************************************************************/
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <crypto/des.h>
|
||||
|
||||
#include "ssi_config.h"
|
||||
#include "ssi_driver.h"
|
||||
#include "cc_hal.h"
|
||||
|
||||
#define FIPS_POWER_UP_TEST_CIPHER 1
|
||||
#define FIPS_POWER_UP_TEST_CMAC 1
|
||||
#define FIPS_POWER_UP_TEST_HASH 1
|
||||
#define FIPS_POWER_UP_TEST_HMAC 1
|
||||
#define FIPS_POWER_UP_TEST_CCM 1
|
||||
#define FIPS_POWER_UP_TEST_GCM 1
|
||||
|
||||
static bool ssi_fips_support = 1;
|
||||
module_param(ssi_fips_support, bool, 0644);
|
||||
MODULE_PARM_DESC(ssi_fips_support, "FIPS supported flag: 0 - off , 1 - on (default)");
|
||||
|
||||
static void fips_dsr(unsigned long devarg);
|
||||
|
||||
struct ssi_fips_handle {
|
||||
#ifdef COMP_IN_WQ
|
||||
struct workqueue_struct *workq;
|
||||
struct delayed_work fipswork;
|
||||
#else
|
||||
struct tasklet_struct fipstask;
|
||||
#endif
|
||||
};
|
||||
|
||||
extern int ssi_fips_get_state(enum cc_fips_state_t *p_state);
|
||||
extern int ssi_fips_get_error(enum cc_fips_error *p_err);
|
||||
extern int ssi_fips_ext_set_state(enum cc_fips_state_t state);
|
||||
extern int ssi_fips_ext_set_error(enum cc_fips_error err);
|
||||
|
||||
/* FIPS power-up tests */
|
||||
extern enum cc_fips_error ssi_cipher_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer);
|
||||
extern enum cc_fips_error ssi_cmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer);
|
||||
extern enum cc_fips_error ssi_hash_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer);
|
||||
extern enum cc_fips_error ssi_hmac_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer);
|
||||
extern enum cc_fips_error ssi_ccm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer);
|
||||
extern enum cc_fips_error ssi_gcm_fips_power_up_tests(struct ssi_drvdata *drvdata, void *cpu_addr_buffer, dma_addr_t dma_coherent_buffer);
|
||||
extern size_t ssi_fips_max_mem_alloc_size(void);
|
||||
|
||||
/* The function called once at driver entry point to check whether TEE FIPS error occured.*/
|
||||
static enum ssi_fips_error ssi_fips_get_tee_error(struct ssi_drvdata *drvdata)
|
||||
{
|
||||
u32 regVal;
|
||||
void __iomem *cc_base = drvdata->cc_base;
|
||||
|
||||
regVal = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GPR_HOST));
|
||||
if (regVal == (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK))
|
||||
return CC_REE_FIPS_ERROR_OK;
|
||||
|
||||
return CC_REE_FIPS_ERROR_FROM_TEE;
|
||||
}
|
||||
|
||||
/*
|
||||
* This function should push the FIPS REE library status towards the TEE library.
|
||||
* By writing the error state to HOST_GPR0 register. The function is called from
|
||||
* driver entry point so no need to protect by mutex.
|
||||
*/
|
||||
static void ssi_fips_update_tee_upon_ree_status(struct ssi_drvdata *drvdata, enum cc_fips_error err)
|
||||
{
|
||||
void __iomem *cc_base = drvdata->cc_base;
|
||||
|
||||
if (err == CC_REE_FIPS_ERROR_OK)
|
||||
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS | CC_FIPS_SYNC_MODULE_OK));
|
||||
else
|
||||
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_GPR0), (CC_FIPS_SYNC_REE_STATUS | CC_FIPS_SYNC_MODULE_ERROR));
|
||||
}
|
||||
|
||||
void ssi_fips_fini(struct ssi_drvdata *drvdata)
|
||||
{
|
||||
struct ssi_fips_handle *fips_h = drvdata->fips_handle;
|
||||
|
||||
if (!fips_h)
|
||||
return; /* Not allocated */
|
||||
|
||||
#ifdef COMP_IN_WQ
|
||||
if (fips_h->workq) {
|
||||
flush_workqueue(fips_h->workq);
|
||||
destroy_workqueue(fips_h->workq);
|
||||
}
|
||||
#else
|
||||
/* Kill tasklet */
|
||||
tasklet_kill(&fips_h->fipstask);
|
||||
#endif
|
||||
memset(fips_h, 0, sizeof(struct ssi_fips_handle));
|
||||
kfree(fips_h);
|
||||
drvdata->fips_handle = NULL;
|
||||
}
|
||||
|
||||
void fips_handler(struct ssi_drvdata *drvdata)
|
||||
{
|
||||
struct ssi_fips_handle *fips_handle_ptr =
|
||||
drvdata->fips_handle;
|
||||
#ifdef COMP_IN_WQ
|
||||
queue_delayed_work(fips_handle_ptr->workq, &fips_handle_ptr->fipswork, 0);
|
||||
#else
|
||||
tasklet_schedule(&fips_handle_ptr->fipstask);
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef COMP_IN_WQ
|
||||
static void fips_wq_handler(struct work_struct *work)
|
||||
{
|
||||
struct ssi_drvdata *drvdata =
|
||||
container_of(work, struct ssi_drvdata, fipswork.work);
|
||||
|
||||
fips_dsr((unsigned long)drvdata);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Deferred service handler, run as interrupt-fired tasklet */
|
||||
static void fips_dsr(unsigned long devarg)
|
||||
{
|
||||
struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg;
|
||||
void __iomem *cc_base = drvdata->cc_base;
|
||||
u32 irq;
|
||||
u32 teeFipsError = 0;
|
||||
|
||||
irq = (drvdata->irq & (SSI_GPR0_IRQ_MASK));
|
||||
|
||||
if (irq & SSI_GPR0_IRQ_MASK) {
|
||||
teeFipsError = CC_HAL_READ_REGISTER(CC_REG_OFFSET(HOST_RGF, GPR_HOST));
|
||||
if (teeFipsError != (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK))
|
||||
ssi_fips_set_error(drvdata, CC_REE_FIPS_ERROR_FROM_TEE);
|
||||
}
|
||||
|
||||
/* after verifing that there is nothing to do, Unmask AXI completion interrupt */
|
||||
CC_HAL_WRITE_REGISTER(CC_REG_OFFSET(HOST_RGF, HOST_IMR),
|
||||
CC_HAL_READ_REGISTER(
|
||||
CC_REG_OFFSET(HOST_RGF, HOST_IMR)) & ~irq);
|
||||
}
|
||||
|
||||
enum cc_fips_error cc_fips_run_power_up_tests(struct ssi_drvdata *drvdata)
|
||||
{
|
||||
enum cc_fips_error fips_error = CC_REE_FIPS_ERROR_OK;
|
||||
void *cpu_addr_buffer = NULL;
|
||||
dma_addr_t dma_handle;
|
||||
size_t alloc_buff_size = ssi_fips_max_mem_alloc_size();
|
||||
struct device *dev = &drvdata->plat_dev->dev;
|
||||
|
||||
// allocate memory using dma_alloc_coherent - for phisical, consecutive and cache coherent buffer (memory map is not needed)
|
||||
// the return value is the virtual address - use it to copy data into the buffer
|
||||
// the dma_handle is the returned phy address - use it in the HW descriptor
|
||||
FIPS_DBG("dma_alloc_coherent \n");
|
||||
cpu_addr_buffer = dma_alloc_coherent(dev, alloc_buff_size, &dma_handle, GFP_KERNEL);
|
||||
if (!cpu_addr_buffer)
|
||||
return CC_REE_FIPS_ERROR_GENERAL;
|
||||
|
||||
FIPS_DBG("allocated coherent buffer - addr 0x%08X , size = %d \n", (size_t)cpu_addr_buffer, alloc_buff_size);
|
||||
|
||||
#if FIPS_POWER_UP_TEST_CIPHER
|
||||
FIPS_DBG("ssi_cipher_fips_power_up_tests ...\n");
|
||||
fips_error = ssi_cipher_fips_power_up_tests(drvdata, cpu_addr_buffer, dma_handle);
|
||||
FIPS_DBG("ssi_cipher_fips_power_up_tests - done. (fips_error = %d) \n", fips_error);
|
||||
#endif
|
||||
#if FIPS_POWER_UP_TEST_CMAC
|
||||
if (likely(fips_error == CC_REE_FIPS_ERROR_OK)) {
|
||||
FIPS_DBG("ssi_cmac_fips_power_up_tests ...\n");
|
||||
fips_error = ssi_cmac_fips_power_up_tests(drvdata, cpu_addr_buffer, dma_handle);
|
||||
FIPS_DBG("ssi_cmac_fips_power_up_tests - done. (fips_error = %d) \n", fips_error);
|
||||
}
|
||||
#endif
|
||||
#if FIPS_POWER_UP_TEST_HASH
|
||||
if (likely(fips_error == CC_REE_FIPS_ERROR_OK)) {
|
||||
FIPS_DBG("ssi_hash_fips_power_up_tests ...\n");
|
||||
fips_error = ssi_hash_fips_power_up_tests(drvdata, cpu_addr_buffer, dma_handle);
|
||||
FIPS_DBG("ssi_hash_fips_power_up_tests - done. (fips_error = %d) \n", fips_error);
|
||||
}
|
||||
#endif
|
||||
#if FIPS_POWER_UP_TEST_HMAC
|
||||
if (likely(fips_error == CC_REE_FIPS_ERROR_OK)) {
|
||||
FIPS_DBG("ssi_hmac_fips_power_up_tests ...\n");
|
||||
fips_error = ssi_hmac_fips_power_up_tests(drvdata, cpu_addr_buffer, dma_handle);
|
||||
FIPS_DBG("ssi_hmac_fips_power_up_tests - done. (fips_error = %d) \n", fips_error);
|
||||
}
|
||||
#endif
|
||||
#if FIPS_POWER_UP_TEST_CCM
|
||||
if (likely(fips_error == CC_REE_FIPS_ERROR_OK)) {
|
||||
FIPS_DBG("ssi_ccm_fips_power_up_tests ...\n");
|
||||
fips_error = ssi_ccm_fips_power_up_tests(drvdata, cpu_addr_buffer, dma_handle);
|
||||
FIPS_DBG("ssi_ccm_fips_power_up_tests - done. (fips_error = %d) \n", fips_error);
|
||||
}
|
||||
#endif
|
||||
#if FIPS_POWER_UP_TEST_GCM
|
||||
if (likely(fips_error == CC_REE_FIPS_ERROR_OK)) {
|
||||
FIPS_DBG("ssi_gcm_fips_power_up_tests ...\n");
|
||||
fips_error = ssi_gcm_fips_power_up_tests(drvdata, cpu_addr_buffer, dma_handle);
|
||||
FIPS_DBG("ssi_gcm_fips_power_up_tests - done. (fips_error = %d) \n", fips_error);
|
||||
}
|
||||
#endif
|
||||
/* deallocate the buffer when all tests are done... */
|
||||
FIPS_DBG("dma_free_coherent \n");
|
||||
dma_free_coherent(dev, alloc_buff_size, cpu_addr_buffer, dma_handle);
|
||||
|
||||
return fips_error;
|
||||
}
|
||||
|
||||
/* The function checks if FIPS supported and FIPS error exists.*
|
||||
* It should be used in every driver API.
|
||||
*/
|
||||
int ssi_fips_check_fips_error(void)
|
||||
{
|
||||
enum cc_fips_state_t fips_state;
|
||||
|
||||
if (ssi_fips_get_state(&fips_state) != 0) {
|
||||
FIPS_LOG("ssi_fips_get_state FAILED, returning.. \n");
|
||||
return -ENOEXEC;
|
||||
}
|
||||
if (fips_state == CC_FIPS_STATE_ERROR) {
|
||||
FIPS_LOG("ssi_fips_get_state: fips_state is %d, returning.. \n", fips_state);
|
||||
return -ENOEXEC;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* The function sets the REE FIPS state.*
|
||||
* It should be used while driver is being loaded.
|
||||
*/
|
||||
int ssi_fips_set_state(enum cc_fips_state_t state)
|
||||
{
|
||||
return ssi_fips_ext_set_state(state);
|
||||
}
|
||||
|
||||
/* The function sets the REE FIPS error, and pushes the error to TEE library. *
|
||||
* It should be used when any of the KAT tests fails.
|
||||
*/
|
||||
int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, enum cc_fips_error err)
|
||||
{
|
||||
int rc = 0;
|
||||
enum cc_fips_error current_err;
|
||||
|
||||
FIPS_LOG("ssi_fips_set_error - fips_error = %d \n", err);
|
||||
|
||||
// setting no error is not allowed
|
||||
if (err == CC_REE_FIPS_ERROR_OK)
|
||||
return -ENOEXEC;
|
||||
|
||||
// If error exists, do not set new error
|
||||
if (ssi_fips_get_error(¤t_err) != 0)
|
||||
return -ENOEXEC;
|
||||
|
||||
if (current_err != CC_REE_FIPS_ERROR_OK)
|
||||
return -ENOEXEC;
|
||||
|
||||
// set REE internal error and state
|
||||
rc = ssi_fips_ext_set_error(err);
|
||||
if (rc != 0)
|
||||
return -ENOEXEC;
|
||||
|
||||
rc = ssi_fips_ext_set_state(CC_FIPS_STATE_ERROR);
|
||||
if (rc != 0)
|
||||
return -ENOEXEC;
|
||||
|
||||
// push error towards TEE libraray, if it's not TEE error
|
||||
if (err != CC_REE_FIPS_ERROR_FROM_TEE)
|
||||
ssi_fips_update_tee_upon_ree_status(p_drvdata, err);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* The function called once at driver entry point .*/
|
||||
int ssi_fips_init(struct ssi_drvdata *p_drvdata)
|
||||
{
|
||||
enum cc_fips_error rc = CC_REE_FIPS_ERROR_OK;
|
||||
struct ssi_fips_handle *fips_h;
|
||||
|
||||
FIPS_DBG("CC FIPS code .. (fips=%d) \n", ssi_fips_support);
|
||||
|
||||
fips_h = kzalloc(sizeof(struct ssi_fips_handle), GFP_KERNEL);
|
||||
if (!fips_h) {
|
||||
ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_GENERAL);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
p_drvdata->fips_handle = fips_h;
|
||||
|
||||
#ifdef COMP_IN_WQ
|
||||
SSI_LOG_DEBUG("Initializing fips workqueue\n");
|
||||
fips_h->workq = create_singlethread_workqueue("arm_cc7x_fips_wq");
|
||||
if (unlikely(!fips_h->workq)) {
|
||||
SSI_LOG_ERR("Failed creating fips work queue\n");
|
||||
ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_GENERAL);
|
||||
rc = -ENOMEM;
|
||||
goto ssi_fips_init_err;
|
||||
}
|
||||
INIT_DELAYED_WORK(&fips_h->fipswork, fips_wq_handler);
|
||||
#else
|
||||
SSI_LOG_DEBUG("Initializing fips tasklet\n");
|
||||
tasklet_init(&fips_h->fipstask, fips_dsr, (unsigned long)p_drvdata);
|
||||
#endif
|
||||
|
||||
/* init fips driver data */
|
||||
rc = ssi_fips_set_state((ssi_fips_support == 0) ? CC_FIPS_STATE_NOT_SUPPORTED : CC_FIPS_STATE_SUPPORTED);
|
||||
if (unlikely(rc != 0)) {
|
||||
ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_GENERAL);
|
||||
rc = -EAGAIN;
|
||||
goto ssi_fips_init_err;
|
||||
}
|
||||
|
||||
/* Run power up tests (before registration and operating the HW engines) */
|
||||
FIPS_DBG("ssi_fips_get_tee_error \n");
|
||||
rc = ssi_fips_get_tee_error(p_drvdata);
|
||||
if (unlikely(rc != CC_REE_FIPS_ERROR_OK)) {
|
||||
ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_FROM_TEE);
|
||||
rc = -EAGAIN;
|
||||
goto ssi_fips_init_err;
|
||||
}
|
||||
|
||||
FIPS_DBG("cc_fips_run_power_up_tests \n");
|
||||
rc = cc_fips_run_power_up_tests(p_drvdata);
|
||||
if (unlikely(rc != CC_REE_FIPS_ERROR_OK)) {
|
||||
ssi_fips_set_error(p_drvdata, rc);
|
||||
rc = -EAGAIN;
|
||||
goto ssi_fips_init_err;
|
||||
}
|
||||
FIPS_LOG("cc_fips_run_power_up_tests - done ... fips_error = %d \n", rc);
|
||||
|
||||
/* when all tests passed, update TEE with fips OK status after power up tests */
|
||||
ssi_fips_update_tee_upon_ree_status(p_drvdata, CC_REE_FIPS_ERROR_OK);
|
||||
|
||||
if (unlikely(rc != 0)) {
|
||||
rc = -EAGAIN;
|
||||
ssi_fips_set_error(p_drvdata, CC_REE_FIPS_ERROR_GENERAL);
|
||||
goto ssi_fips_init_err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
ssi_fips_init_err:
|
||||
ssi_fips_fini(p_drvdata);
|
||||
return rc;
|
||||
}
|
||||
|
||||
@ -1,67 +0,0 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2017 ARM Limited or its affiliates.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __SSI_FIPS_LOCAL_H__
|
||||
#define __SSI_FIPS_LOCAL_H__
|
||||
|
||||
#ifdef CONFIG_CCX7REE_FIPS_SUPPORT
|
||||
|
||||
#include "ssi_fips.h"
|
||||
struct ssi_drvdata;
|
||||
|
||||
#define CHECK_AND_RETURN_UPON_FIPS_ERROR() {\
|
||||
if (ssi_fips_check_fips_error() != 0) {\
|
||||
return -ENOEXEC;\
|
||||
} \
|
||||
}
|
||||
|
||||
#define CHECK_AND_RETURN_VOID_UPON_FIPS_ERROR() {\
|
||||
if (ssi_fips_check_fips_error() != 0) {\
|
||||
return;\
|
||||
} \
|
||||
}
|
||||
|
||||
#define SSI_FIPS_INIT(p_drvData) (ssi_fips_init(p_drvData))
|
||||
#define SSI_FIPS_FINI(p_drvData) (ssi_fips_fini(p_drvData))
|
||||
|
||||
#define FIPS_LOG(...) SSI_LOG(KERN_INFO, __VA_ARGS__)
|
||||
#define FIPS_DBG(...) //SSI_LOG(KERN_INFO, __VA_ARGS__)
|
||||
|
||||
/* FIPS functions */
|
||||
int ssi_fips_init(struct ssi_drvdata *p_drvdata);
|
||||
void ssi_fips_fini(struct ssi_drvdata *drvdata);
|
||||
int ssi_fips_check_fips_error(void);
|
||||
int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, enum cc_fips_error err);
|
||||
void fips_handler(struct ssi_drvdata *drvdata);
|
||||
|
||||
#else /* CONFIG_CC7XXREE_FIPS_SUPPORT */
|
||||
|
||||
#define CHECK_AND_RETURN_UPON_FIPS_ERROR()
|
||||
#define CHECK_AND_RETURN_VOID_UPON_FIPS_ERROR()
|
||||
|
||||
static inline int ssi_fips_init(struct ssi_drvdata *p_drvdata)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void ssi_fips_fini(struct ssi_drvdata *drvdata) {}
|
||||
|
||||
void fips_handler(struct ssi_drvdata *drvdata);
|
||||
|
||||
#endif /* CONFIG_CC7XXREE_FIPS_SUPPORT */
|
||||
|
||||
#endif /*__SSI_FIPS_LOCAL_H__*/
|
||||
|
||||
@ -30,7 +30,6 @@
|
||||
#include "ssi_sysfs.h"
|
||||
#include "ssi_hash.h"
|
||||
#include "ssi_sram_mgr.h"
|
||||
#include "ssi_fips_local.h"
|
||||
|
||||
#define SSI_MAX_AHASH_SEQ_LEN 12
|
||||
#define SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE MAX(SSI_MAX_HASH_BLCK_SIZE, 3 * AES_BLOCK_SIZE)
|
||||
@ -431,8 +430,6 @@ static int ssi_hash_digest(struct ahash_req_ctx *state,
|
||||
|
||||
SSI_LOG_DEBUG("===== %s-digest (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
if (unlikely(ssi_hash_map_request(dev, state, ctx) != 0)) {
|
||||
SSI_LOG_ERR("map_ahash_source() failed\n");
|
||||
return -ENOMEM;
|
||||
@ -596,7 +593,6 @@ static int ssi_hash_update(struct ahash_req_ctx *state,
|
||||
SSI_LOG_DEBUG("===== %s-update (%d) ====\n", ctx->is_hmac ?
|
||||
"hmac" : "hash", nbytes);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
if (nbytes == 0) {
|
||||
/* no real updates required */
|
||||
return 0;
|
||||
@ -694,8 +690,6 @@ static int ssi_hash_finup(struct ahash_req_ctx *state,
|
||||
|
||||
SSI_LOG_DEBUG("===== %s-finup (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 1) != 0)) {
|
||||
SSI_LOG_ERR("map_ahash_request_final() failed\n");
|
||||
return -ENOMEM;
|
||||
@ -830,8 +824,6 @@ static int ssi_hash_final(struct ahash_req_ctx *state,
|
||||
|
||||
SSI_LOG_DEBUG("===== %s-final (%d) ====\n", is_hmac ? "hmac" : "hash", nbytes);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
if (unlikely(ssi_buffer_mgr_map_hash_request_final(ctx->drvdata, state, src, nbytes, 0) != 0)) {
|
||||
SSI_LOG_ERR("map_ahash_request_final() failed\n");
|
||||
return -ENOMEM;
|
||||
@ -965,7 +957,6 @@ static int ssi_hash_init(struct ahash_req_ctx *state, struct ssi_hash_ctx *ctx)
|
||||
|
||||
state->xcbc_count = 0;
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
ssi_hash_map_request(dev, state, ctx);
|
||||
|
||||
return 0;
|
||||
@ -987,7 +978,6 @@ static int ssi_hash_setkey(void *hash,
|
||||
|
||||
SSI_LOG_DEBUG("ssi_hash_setkey: start keylen: %d", keylen);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
ctx = crypto_ahash_ctx(((struct crypto_ahash *)hash));
|
||||
blocksize = crypto_tfm_alg_blocksize(&((struct crypto_ahash *)hash)->base);
|
||||
digestsize = crypto_ahash_digestsize(((struct crypto_ahash *)hash));
|
||||
@ -1174,7 +1164,6 @@ static int ssi_xcbc_setkey(struct crypto_ahash *ahash,
|
||||
struct cc_hw_desc desc[SSI_MAX_AHASH_SEQ_LEN];
|
||||
|
||||
SSI_LOG_DEBUG("===== setkey (%d) ====\n", keylen);
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
switch (keylen) {
|
||||
case AES_KEYSIZE_128:
|
||||
@ -1260,7 +1249,6 @@ static int ssi_cmac_setkey(struct crypto_ahash *ahash,
|
||||
struct ssi_hash_ctx *ctx = crypto_ahash_ctx(ahash);
|
||||
|
||||
SSI_LOG_DEBUG("===== setkey (%d) ====\n", keylen);
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
ctx->is_hmac = true;
|
||||
|
||||
@ -1365,7 +1353,6 @@ static int ssi_ahash_cra_init(struct crypto_tfm *tfm)
|
||||
struct ssi_hash_alg *ssi_alg =
|
||||
container_of(ahash_alg, struct ssi_hash_alg, ahash_alg);
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
|
||||
sizeof(struct ahash_req_ctx));
|
||||
|
||||
@ -1397,7 +1384,6 @@ static int ssi_mac_update(struct ahash_request *req)
|
||||
int rc;
|
||||
u32 idx = 0;
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
if (req->nbytes == 0) {
|
||||
/* no real updates required */
|
||||
return 0;
|
||||
@ -1462,7 +1448,6 @@ static int ssi_mac_final(struct ahash_request *req)
|
||||
u32 rem_cnt = state->buff_index ? state->buff1_cnt :
|
||||
state->buff0_cnt;
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
if (ctx->hw_mode == DRV_CIPHER_XCBC_MAC) {
|
||||
keySize = CC_AES_128_BIT_KEY_SIZE;
|
||||
keyLen = CC_AES_128_BIT_KEY_SIZE;
|
||||
@ -1571,7 +1556,6 @@ static int ssi_mac_finup(struct ahash_request *req)
|
||||
u32 digestsize = crypto_ahash_digestsize(tfm);
|
||||
|
||||
SSI_LOG_DEBUG("===== finup xcbc(%d) ====\n", req->nbytes);
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
if (state->xcbc_count > 0 && req->nbytes == 0) {
|
||||
SSI_LOG_DEBUG("No data to update. Call to fdx_mac_final \n");
|
||||
return ssi_mac_final(req);
|
||||
@ -1643,7 +1627,6 @@ static int ssi_mac_digest(struct ahash_request *req)
|
||||
int rc;
|
||||
|
||||
SSI_LOG_DEBUG("===== -digest mac (%d) ====\n", req->nbytes);
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
if (unlikely(ssi_hash_map_request(dev, state, ctx) != 0)) {
|
||||
SSI_LOG_ERR("map_ahash_source() failed\n");
|
||||
@ -1766,8 +1749,6 @@ static int ssi_ahash_export(struct ahash_request *req, void *out)
|
||||
state->buff0_cnt;
|
||||
const u32 tmp = CC_EXPORT_MAGIC;
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
memcpy(out, &tmp, sizeof(u32));
|
||||
out += sizeof(u32);
|
||||
|
||||
@ -1807,8 +1788,6 @@ static int ssi_ahash_import(struct ahash_request *req, const void *in)
|
||||
u32 tmp;
|
||||
int rc;
|
||||
|
||||
CHECK_AND_RETURN_UPON_FIPS_ERROR();
|
||||
|
||||
memcpy(&tmp, in, sizeof(u32));
|
||||
if (tmp != CC_EXPORT_MAGIC) {
|
||||
rc = -EINVAL;
|
||||
|
||||
@ -30,8 +30,6 @@
|
||||
#include "ssi_sysfs.h"
|
||||
#include "ssi_ivgen.h"
|
||||
#include "ssi_pm.h"
|
||||
#include "ssi_fips.h"
|
||||
#include "ssi_fips_local.h"
|
||||
|
||||
#define SSI_MAX_POLL_ITER 10
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user