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https://github.com/torvalds/linux.git
synced 2024-11-27 14:41:39 +00:00
S2io: Fixes to enable multiple transmit fifos
Multiple transmit fifo initialization -
- Assigned equal scheduling priority for all configured FIFO's.
- Modularized transmit traffic interrupt initialization since it is executed in
s2io_card_up and s2io_link. Enable continuous tx interrupt when link is UP
and vice verse.
- Enable transmit interrupts for all configured transmit fifos.
- Fixed typo errors.
Signed-off-by: Surjit Reang <surjit.reang@neterion.com>
Signed-off-by: Sreenivasa Honnur <sreenivasa.honnur@neterion.com>
Signed-off-by: Ramkrishna Vepa <ram.vepa@neterion.com>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Ramkrishna Vepa
David S. Miller
parent
2fda096d18
commit
b7c5678f0b
@ -84,7 +84,7 @@
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#include "s2io.h"
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#include "s2io-regs.h"
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#define DRV_VERSION "2.0.26.15-1"
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#define DRV_VERSION "2.0.26.15-2"
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/* S2io Driver name & version. */
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static char s2io_driver_name[] = "Neterion";
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@ -1078,9 +1078,68 @@ static int s2io_print_pci_mode(struct s2io_nic *nic)
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return mode;
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}
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/**
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* init_tti - Initialization transmit traffic interrupt scheme
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* @nic: device private variable
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* @link: link status (UP/DOWN) used to enable/disable continuous
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* transmit interrupts
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* Description: The function configures transmit traffic interrupts
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* Return Value: SUCCESS on success and
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* '-1' on failure
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*/
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int init_tti(struct s2io_nic *nic, int link)
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{
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struct XENA_dev_config __iomem *bar0 = nic->bar0;
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register u64 val64 = 0;
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int i;
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struct config_param *config;
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config = &nic->config;
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for (i = 0; i < config->tx_fifo_num; i++) {
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/*
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* TTI Initialization. Default Tx timer gets us about
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* 250 interrupts per sec. Continuous interrupts are enabled
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* by default.
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*/
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if (nic->device_type == XFRAME_II_DEVICE) {
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int count = (nic->config.bus_speed * 125)/2;
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val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
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} else
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val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
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val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
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TTI_DATA1_MEM_TX_URNG_B(0x10) |
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TTI_DATA1_MEM_TX_URNG_C(0x30) |
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TTI_DATA1_MEM_TX_TIMER_AC_EN;
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if (use_continuous_tx_intrs && (link == LINK_UP))
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val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
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writeq(val64, &bar0->tti_data1_mem);
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val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
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TTI_DATA2_MEM_TX_UFC_B(0x20) |
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TTI_DATA2_MEM_TX_UFC_C(0x40) |
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TTI_DATA2_MEM_TX_UFC_D(0x80);
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writeq(val64, &bar0->tti_data2_mem);
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val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
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TTI_CMD_MEM_OFFSET(i);
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writeq(val64, &bar0->tti_command_mem);
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if (wait_for_cmd_complete(&bar0->tti_command_mem,
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TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
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return FAILURE;
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}
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return SUCCESS;
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}
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/**
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* init_nic - Initialization of hardware
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* @nic: device peivate variable
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* @nic: device private variable
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* Description: The function sequentially configures every block
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* of the H/W from their reset values.
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* Return Value: SUCCESS on success and
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@ -1185,9 +1244,9 @@ static int init_nic(struct s2io_nic *nic)
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for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
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val64 |=
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vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
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vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
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13) | vBIT(config->tx_cfg[i].fifo_priority,
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((i * 32) + 5), 3);
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((j * 32) + 5), 3);
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if (i == (config->tx_fifo_num - 1)) {
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if (i % 2 == 0)
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@ -1198,17 +1257,25 @@ static int init_nic(struct s2io_nic *nic)
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case 1:
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writeq(val64, &bar0->tx_fifo_partition_0);
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val64 = 0;
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j = 0;
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break;
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case 3:
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writeq(val64, &bar0->tx_fifo_partition_1);
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val64 = 0;
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j = 0;
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break;
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case 5:
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writeq(val64, &bar0->tx_fifo_partition_2);
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val64 = 0;
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j = 0;
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break;
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case 7:
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writeq(val64, &bar0->tx_fifo_partition_3);
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val64 = 0;
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j = 0;
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break;
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default:
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j++;
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break;
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}
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}
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@ -1294,11 +1361,11 @@ static int init_nic(struct s2io_nic *nic)
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/*
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* Filling Tx round robin registers
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* as per the number of FIFOs
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* as per the number of FIFOs for equal scheduling priority
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*/
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switch (config->tx_fifo_num) {
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case 1:
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val64 = 0x0000000000000000ULL;
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val64 = 0x0;
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writeq(val64, &bar0->tx_w_round_robin_0);
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writeq(val64, &bar0->tx_w_round_robin_1);
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writeq(val64, &bar0->tx_w_round_robin_2);
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@ -1306,87 +1373,78 @@ static int init_nic(struct s2io_nic *nic)
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writeq(val64, &bar0->tx_w_round_robin_4);
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break;
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case 2:
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val64 = 0x0000010000010000ULL;
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val64 = 0x0001000100010001ULL;
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writeq(val64, &bar0->tx_w_round_robin_0);
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val64 = 0x0100000100000100ULL;
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writeq(val64, &bar0->tx_w_round_robin_1);
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val64 = 0x0001000001000001ULL;
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writeq(val64, &bar0->tx_w_round_robin_2);
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val64 = 0x0000010000010000ULL;
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writeq(val64, &bar0->tx_w_round_robin_3);
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val64 = 0x0100000000000000ULL;
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val64 = 0x0001000100000000ULL;
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writeq(val64, &bar0->tx_w_round_robin_4);
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break;
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case 3:
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val64 = 0x0001000102000001ULL;
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val64 = 0x0001020001020001ULL;
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writeq(val64, &bar0->tx_w_round_robin_0);
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val64 = 0x0001020000010001ULL;
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val64 = 0x0200010200010200ULL;
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writeq(val64, &bar0->tx_w_round_robin_1);
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val64 = 0x0200000100010200ULL;
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val64 = 0x0102000102000102ULL;
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writeq(val64, &bar0->tx_w_round_robin_2);
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val64 = 0x0001000102000001ULL;
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val64 = 0x0001020001020001ULL;
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writeq(val64, &bar0->tx_w_round_robin_3);
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val64 = 0x0001020000000000ULL;
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val64 = 0x0200010200000000ULL;
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writeq(val64, &bar0->tx_w_round_robin_4);
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break;
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case 4:
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val64 = 0x0001020300010200ULL;
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val64 = 0x0001020300010203ULL;
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writeq(val64, &bar0->tx_w_round_robin_0);
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val64 = 0x0100000102030001ULL;
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writeq(val64, &bar0->tx_w_round_robin_1);
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val64 = 0x0200010000010203ULL;
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writeq(val64, &bar0->tx_w_round_robin_2);
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val64 = 0x0001020001000001ULL;
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writeq(val64, &bar0->tx_w_round_robin_3);
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val64 = 0x0203000100000000ULL;
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val64 = 0x0001020300000000ULL;
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writeq(val64, &bar0->tx_w_round_robin_4);
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break;
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case 5:
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val64 = 0x0001000203000102ULL;
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val64 = 0x0001020304000102ULL;
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writeq(val64, &bar0->tx_w_round_robin_0);
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val64 = 0x0001020001030004ULL;
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val64 = 0x0304000102030400ULL;
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writeq(val64, &bar0->tx_w_round_robin_1);
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val64 = 0x0001000203000102ULL;
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val64 = 0x0102030400010203ULL;
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writeq(val64, &bar0->tx_w_round_robin_2);
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val64 = 0x0001020001030004ULL;
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val64 = 0x0400010203040001ULL;
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writeq(val64, &bar0->tx_w_round_robin_3);
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val64 = 0x0001000000000000ULL;
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val64 = 0x0203040000000000ULL;
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writeq(val64, &bar0->tx_w_round_robin_4);
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break;
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case 6:
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val64 = 0x0001020304000102ULL;
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val64 = 0x0001020304050001ULL;
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writeq(val64, &bar0->tx_w_round_robin_0);
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val64 = 0x0304050001020001ULL;
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val64 = 0x0203040500010203ULL;
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writeq(val64, &bar0->tx_w_round_robin_1);
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val64 = 0x0203000100000102ULL;
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val64 = 0x0405000102030405ULL;
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writeq(val64, &bar0->tx_w_round_robin_2);
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val64 = 0x0304000102030405ULL;
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val64 = 0x0001020304050001ULL;
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writeq(val64, &bar0->tx_w_round_robin_3);
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val64 = 0x0001000200000000ULL;
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val64 = 0x0203040500000000ULL;
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writeq(val64, &bar0->tx_w_round_robin_4);
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break;
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case 7:
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val64 = 0x0001020001020300ULL;
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val64 = 0x0001020304050600ULL;
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writeq(val64, &bar0->tx_w_round_robin_0);
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val64 = 0x0102030400010203ULL;
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val64 = 0x0102030405060001ULL;
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writeq(val64, &bar0->tx_w_round_robin_1);
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val64 = 0x0405060001020001ULL;
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val64 = 0x0203040506000102ULL;
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writeq(val64, &bar0->tx_w_round_robin_2);
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val64 = 0x0304050000010200ULL;
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val64 = 0x0304050600010203ULL;
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writeq(val64, &bar0->tx_w_round_robin_3);
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val64 = 0x0102030000000000ULL;
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val64 = 0x0405060000000000ULL;
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writeq(val64, &bar0->tx_w_round_robin_4);
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break;
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case 8:
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val64 = 0x0001020300040105ULL;
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val64 = 0x0001020304050607ULL;
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writeq(val64, &bar0->tx_w_round_robin_0);
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val64 = 0x0200030106000204ULL;
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writeq(val64, &bar0->tx_w_round_robin_1);
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val64 = 0x0103000502010007ULL;
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writeq(val64, &bar0->tx_w_round_robin_2);
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val64 = 0x0304010002060500ULL;
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writeq(val64, &bar0->tx_w_round_robin_3);
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val64 = 0x0103020400000000ULL;
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val64 = 0x0001020300000000ULL;
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writeq(val64, &bar0->tx_w_round_robin_4);
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break;
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}
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@ -1563,58 +1621,14 @@ static int init_nic(struct s2io_nic *nic)
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MAC_RX_LINK_UTIL_VAL(rmac_util_period);
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writeq(val64, &bar0->mac_link_util);
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/*
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* Initializing the Transmit and Receive Traffic Interrupt
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* Scheme.
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*/
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/*
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* TTI Initialization. Default Tx timer gets us about
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* 250 interrupts per sec. Continuous interrupts are enabled
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* by default.
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*/
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if (nic->device_type == XFRAME_II_DEVICE) {
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int count = (nic->config.bus_speed * 125)/2;
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val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
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} else {
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val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
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}
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val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
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TTI_DATA1_MEM_TX_URNG_B(0x10) |
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TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
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if (use_continuous_tx_intrs)
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val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
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writeq(val64, &bar0->tti_data1_mem);
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val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
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TTI_DATA2_MEM_TX_UFC_B(0x20) |
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TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
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writeq(val64, &bar0->tti_data2_mem);
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val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
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writeq(val64, &bar0->tti_command_mem);
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/*
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* Once the operation completes, the Strobe bit of the command
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* register will be reset. We poll for this particular condition
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* We wait for a maximum of 500ms for the operation to complete,
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* if it's not complete by then we return error.
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*/
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time = 0;
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while (TRUE) {
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val64 = readq(&bar0->tti_command_mem);
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if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
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break;
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}
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if (time > 10) {
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DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
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dev->name);
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return -ENODEV;
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}
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msleep(50);
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time++;
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}
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/* Initialize TTI */
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if (SUCCESS != init_tti(nic, nic->last_link_state))
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return -ENODEV;
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/* RTI Initialization */
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if (nic->device_type == XFRAME_II_DEVICE) {
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@ -7443,6 +7457,7 @@ static void s2io_link(struct s2io_nic * sp, int link)
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struct net_device *dev = (struct net_device *) sp->dev;
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if (link != sp->last_link_state) {
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init_tti(sp, link);
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if (link == LINK_DOWN) {
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DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
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netif_carrier_off(dev);
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@ -7541,7 +7556,7 @@ static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
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/**
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* rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
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* or Traffic class respectively.
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* @nic: device peivate variable
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* @nic: device private variable
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* Description: The function configures the receive steering to
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* desired receive ring.
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* Return Value: SUCCESS on success and
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