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crypto: mediatek - add MTK_* prefix and correct annotations.

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Dummy patch to add MTK_* prefix to ring enum and fix incorrect annotations.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Ryder Lee 2017-03-09 10:11:13 +08:00 committed by Herbert Xu
parent 132c57caef
commit b7a2be388b
4 changed files with 32 additions and 32 deletions
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12
drivers/crypto/mediatek/mtk-aes.c
View File

@ -1152,8 +1152,8 @@ static int mtk_aes_record_init(struct mtk_cryp *cryp)
} }
/* Link to ring0 and ring1 respectively */ /* Link to ring0 and ring1 respectively */
aes[0]->id = RING0; aes[0]->id = MTK_RING0;
aes[1]->id = RING1; aes[1]->id = MTK_RING1;
return 0; return 0;
@ -1221,14 +1221,14 @@ int mtk_cipher_alg_register(struct mtk_cryp *cryp)
if (ret) if (ret)
goto err_record; goto err_record;
ret = devm_request_irq(cryp->dev, cryp->irq[RING0], mtk_aes_irq, ret = devm_request_irq(cryp->dev, cryp->irq[MTK_RING0], mtk_aes_irq,
0, "mtk-aes", cryp->aes[0]); 0, "mtk-aes", cryp->aes[0]);
if (ret) { if (ret) {
dev_err(cryp->dev, "unable to request AES irq.\n"); dev_err(cryp->dev, "unable to request AES irq.\n");
goto err_res; goto err_res;
} }
ret = devm_request_irq(cryp->dev, cryp->irq[RING1], mtk_aes_irq, ret = devm_request_irq(cryp->dev, cryp->irq[MTK_RING1], mtk_aes_irq,
0, "mtk-aes", cryp->aes[1]); 0, "mtk-aes", cryp->aes[1]);
if (ret) { if (ret) {
dev_err(cryp->dev, "unable to request AES irq.\n"); dev_err(cryp->dev, "unable to request AES irq.\n");
@ -1236,8 +1236,8 @@ int mtk_cipher_alg_register(struct mtk_cryp *cryp)
} }
/* Enable ring0 and ring1 interrupt */ /* Enable ring0 and ring1 interrupt */
mtk_aes_write(cryp, AIC_ENABLE_SET(RING0), MTK_IRQ_RDR0); mtk_aes_write(cryp, AIC_ENABLE_SET(MTK_RING0), MTK_IRQ_RDR0);
mtk_aes_write(cryp, AIC_ENABLE_SET(RING1), MTK_IRQ_RDR1); mtk_aes_write(cryp, AIC_ENABLE_SET(MTK_RING1), MTK_IRQ_RDR1);
spin_lock(&mtk_aes.lock); spin_lock(&mtk_aes.lock);
list_add_tail(&cryp->aes_list, &mtk_aes.dev_list); list_add_tail(&cryp->aes_list, &mtk_aes.dev_list);

12
drivers/crypto/mediatek/mtk-platform.c
View File

@ -334,7 +334,7 @@ static int mtk_packet_engine_setup(struct mtk_cryp *cryp)
/* Enable the 4 rings for the packet engines. */ /* Enable the 4 rings for the packet engines. */
mtk_desc_ring_link(cryp, 0xf); mtk_desc_ring_link(cryp, 0xf);
for (i = 0; i < RING_MAX; i++) { for (i = 0; i < MTK_RING_MAX; i++) {
mtk_cmd_desc_ring_setup(cryp, i, &cap); mtk_cmd_desc_ring_setup(cryp, i, &cap);
mtk_res_desc_ring_setup(cryp, i, &cap); mtk_res_desc_ring_setup(cryp, i, &cap);
} }
@ -359,7 +359,7 @@ static int mtk_aic_cap_check(struct mtk_cryp *cryp, int hw)
{ {
u32 val; u32 val;
if (hw == RING_MAX) if (hw == MTK_RING_MAX)
val = readl(cryp->base + AIC_G_VERSION); val = readl(cryp->base + AIC_G_VERSION);
else else
val = readl(cryp->base + AIC_VERSION(hw)); val = readl(cryp->base + AIC_VERSION(hw));
@ -368,7 +368,7 @@ static int mtk_aic_cap_check(struct mtk_cryp *cryp, int hw)
if (val != MTK_AIC_VER11 && val != MTK_AIC_VER12) if (val != MTK_AIC_VER11 && val != MTK_AIC_VER12)
return -ENXIO; return -ENXIO;
if (hw == RING_MAX) if (hw == MTK_RING_MAX)
val = readl(cryp->base + AIC_G_OPTIONS); val = readl(cryp->base + AIC_G_OPTIONS);
else else
val = readl(cryp->base + AIC_OPTIONS(hw)); val = readl(cryp->base + AIC_OPTIONS(hw));
@ -389,7 +389,7 @@ static int mtk_aic_init(struct mtk_cryp *cryp, int hw)
return err; return err;
/* Disable all interrupts and set initial configuration */ /* Disable all interrupts and set initial configuration */
if (hw == RING_MAX) { if (hw == MTK_RING_MAX) {
writel(0, cryp->base + AIC_G_ENABLE_CTRL); writel(0, cryp->base + AIC_G_ENABLE_CTRL);
writel(0, cryp->base + AIC_G_POL_CTRL); writel(0, cryp->base + AIC_G_POL_CTRL);
writel(0, cryp->base + AIC_G_TYPE_CTRL); writel(0, cryp->base + AIC_G_TYPE_CTRL);
@ -431,7 +431,7 @@ static void mtk_desc_dma_free(struct mtk_cryp *cryp)
{ {
int i; int i;
for (i = 0; i < RING_MAX; i++) { for (i = 0; i < MTK_RING_MAX; i++) {
dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ, dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
cryp->ring[i]->res_base, cryp->ring[i]->res_base,
cryp->ring[i]->res_dma); cryp->ring[i]->res_dma);
@ -447,7 +447,7 @@ static int mtk_desc_ring_alloc(struct mtk_cryp *cryp)
struct mtk_ring **ring = cryp->ring; struct mtk_ring **ring = cryp->ring;
int i, err = ENOMEM; int i, err = ENOMEM;
for (i = 0; i < RING_MAX; i++) { for (i = 0; i < MTK_RING_MAX; i++) {
ring[i] = kzalloc(sizeof(**ring), GFP_KERNEL); ring[i] = kzalloc(sizeof(**ring), GFP_KERNEL);
if (!ring[i]) if (!ring[i])
goto err_cleanup; goto err_cleanup;

26
drivers/crypto/mediatek/mtk-platform.h
View File

@ -38,14 +38,14 @@
* Ring 2/3 are used by SHA. * Ring 2/3 are used by SHA.
*/ */
enum { enum {
RING0 = 0, MTK_RING0,
RING1, MTK_RING1,
RING2, MTK_RING2,
RING3, MTK_RING3,
RING_MAX, MTK_RING_MAX
}; };
#define MTK_REC_NUM (RING_MAX / 2) #define MTK_REC_NUM (MTK_RING_MAX / 2)
#define MTK_IRQ_NUM 5 #define MTK_IRQ_NUM 5
/** /**
@ -137,7 +137,7 @@ typedef int (*mtk_aes_fn)(struct mtk_cryp *cryp, struct mtk_aes_rec *aes);
* @resume: pointer to resume function * @resume: pointer to resume function
* @total: request buffer length * @total: request buffer length
* @buf: pointer to page buffer * @buf: pointer to page buffer
* @id: record identification * @id: the current use of ring
* @flags: it's describing AES operation state * @flags: it's describing AES operation state
* @lock: the async queue lock * @lock: the async queue lock
* *
@ -172,9 +172,9 @@ struct mtk_aes_rec {
* @queue: crypto request queue * @queue: crypto request queue
* @req: pointer to ahash request * @req: pointer to ahash request
* @task: the tasklet is use in SHA interrupt * @task: the tasklet is use in SHA interrupt
* @id: record identification * @id: the current use of ring
* @flags: it's describing SHA operation state * @flags: it's describing SHA operation state
* @lock: the ablkcipher queue lock * @lock: the async queue lock
* *
* Structure used to record SHA execution state. * Structure used to record SHA execution state.
*/ */
@ -197,9 +197,9 @@ struct mtk_sha_rec {
* @clk_ethif: pointer to ethif clock * @clk_ethif: pointer to ethif clock
* @clk_cryp: pointer to crypto clock * @clk_cryp: pointer to crypto clock
* @irq: global system and rings IRQ * @irq: global system and rings IRQ
* @ring: pointer to execution state of AES * @ring: pointer to descriptor rings
* @aes: pointer to execution state of SHA * @aes: pointer to operation record of AES
* @sha: each execution record map to a ring * @sha: pointer to operation record of SHA
* @aes_list: device list of AES * @aes_list: device list of AES
* @sha_list: device list of SHA * @sha_list: device list of SHA
* @tmp: pointer to temporary buffer for internal use * @tmp: pointer to temporary buffer for internal use
@ -215,7 +215,7 @@ struct mtk_cryp {
struct clk *clk_cryp; struct clk *clk_cryp;
int irq[MTK_IRQ_NUM]; int irq[MTK_IRQ_NUM];
struct mtk_ring *ring[RING_MAX]; struct mtk_ring *ring[MTK_RING_MAX];
struct mtk_aes_rec *aes[MTK_REC_NUM]; struct mtk_aes_rec *aes[MTK_REC_NUM];
struct mtk_sha_rec *sha[MTK_REC_NUM]; struct mtk_sha_rec *sha[MTK_REC_NUM];

14
drivers/crypto/mediatek/mtk-sha.c
View File

@ -694,7 +694,7 @@ static void mtk_sha_finish_req(struct mtk_cryp *cryp,
sha->req->base.complete(&sha->req->base, err); sha->req->base.complete(&sha->req->base, err);
/* Handle new request */ /* Handle new request */
mtk_sha_handle_queue(cryp, sha->id - RING2, NULL); mtk_sha_handle_queue(cryp, sha->id - MTK_RING2, NULL);
} }
static int mtk_sha_handle_queue(struct mtk_cryp *cryp, u8 id, static int mtk_sha_handle_queue(struct mtk_cryp *cryp, u8 id,
@ -1269,8 +1269,8 @@ static int mtk_sha_record_init(struct mtk_cryp *cryp)
} }
/* Link to ring2 and ring3 respectively */ /* Link to ring2 and ring3 respectively */
sha[0]->id = RING2; sha[0]->id = MTK_RING2;
sha[1]->id = RING3; sha[1]->id = MTK_RING3;
cryp->rec = 1; cryp->rec = 1;
@ -1343,14 +1343,14 @@ int mtk_hash_alg_register(struct mtk_cryp *cryp)
if (err) if (err)
goto err_record; goto err_record;
err = devm_request_irq(cryp->dev, cryp->irq[RING2], mtk_sha_irq, err = devm_request_irq(cryp->dev, cryp->irq[MTK_RING2], mtk_sha_irq,
0, "mtk-sha", cryp->sha[0]); 0, "mtk-sha", cryp->sha[0]);
if (err) { if (err) {
dev_err(cryp->dev, "unable to request sha irq0.\n"); dev_err(cryp->dev, "unable to request sha irq0.\n");
goto err_res; goto err_res;
} }
err = devm_request_irq(cryp->dev, cryp->irq[RING3], mtk_sha_irq, err = devm_request_irq(cryp->dev, cryp->irq[MTK_RING3], mtk_sha_irq,
0, "mtk-sha", cryp->sha[1]); 0, "mtk-sha", cryp->sha[1]);
if (err) { if (err) {
dev_err(cryp->dev, "unable to request sha irq1.\n"); dev_err(cryp->dev, "unable to request sha irq1.\n");
@ -1358,8 +1358,8 @@ int mtk_hash_alg_register(struct mtk_cryp *cryp)
} }
/* Enable ring2 and ring3 interrupt for hash */ /* Enable ring2 and ring3 interrupt for hash */
mtk_sha_write(cryp, AIC_ENABLE_SET(RING2), MTK_IRQ_RDR2); mtk_sha_write(cryp, AIC_ENABLE_SET(MTK_RING2), MTK_IRQ_RDR2);
mtk_sha_write(cryp, AIC_ENABLE_SET(RING3), MTK_IRQ_RDR3); mtk_sha_write(cryp, AIC_ENABLE_SET(MTK_RING3), MTK_IRQ_RDR3);
cryp->tmp = dma_alloc_coherent(cryp->dev, SHA_TMP_BUF_SIZE, cryp->tmp = dma_alloc_coherent(cryp->dev, SHA_TMP_BUF_SIZE,
&cryp->tmp_dma, GFP_KERNEL); &cryp->tmp_dma, GFP_KERNEL);