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Merge branch 'next/pinctrl-exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers
From Kukjin Kim <kgene.kim@samsung.com>: Here is support pinctrl-exynos5250 and that already got ack from Linus Walleij. * 'next/pinctrl-exynos' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: EXYNOS: skip wakeup interrupt registration for exynos5250 if pinctrl is enabled gpio: samsung: skip gpiolib registration if pinctrl support is enabled for exynos5250 pinctrl: exynos: add exynos5250 SoC specific data Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
b7442b6c8b
@ -822,6 +822,7 @@ static int __init exynos_init_irq_eint(void)
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static const struct of_device_id exynos_pinctrl_ids[] = {
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{ .compatible = "samsung,exynos4210-pinctrl", },
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{ .compatible = "samsung,exynos4x12-pinctrl", },
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{ .compatible = "samsung,exynos5250-pinctrl", },
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};
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struct device_node *pctrl_np, *wkup_np;
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const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
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@ -3028,6 +3028,7 @@ static __init int samsung_gpiolib_init(void)
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static const struct of_device_id exynos_pinctrl_ids[] = {
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{ .compatible = "samsung,exynos4210-pinctrl", },
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{ .compatible = "samsung,exynos4x12-pinctrl", },
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{ .compatible = "samsung,exynos5250-pinctrl", },
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{ .compatible = "samsung,exynos5440-pinctrl", },
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};
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for_each_matching_node(pctrl_np, exynos_pinctrl_ids)
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@ -677,3 +677,111 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
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.label = "exynos4x12-gpio-ctrl3",
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},
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};
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/* pin banks of exynos5250 pin-controller 0 */
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static struct samsung_pin_bank exynos5250_pin_banks0[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
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EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
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EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
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EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
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EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
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EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
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EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
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EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
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EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
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EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
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EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
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EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
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EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
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EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
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EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
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EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
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EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
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EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
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EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
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EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
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EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
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EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
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EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
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EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
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};
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/* pin banks of exynos5250 pin-controller 1 */
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static struct samsung_pin_bank exynos5250_pin_banks1[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
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EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
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EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
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EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
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EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
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EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
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EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
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EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
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EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
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};
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/* pin banks of exynos5250 pin-controller 2 */
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static struct samsung_pin_bank exynos5250_pin_banks2[] = {
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EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
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EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
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EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
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EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
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EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
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};
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/* pin banks of exynos5250 pin-controller 3 */
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static struct samsung_pin_bank exynos5250_pin_banks3[] = {
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EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
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};
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/*
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* Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
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* four gpio/pin-mux/pinconfig controllers.
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*/
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struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
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{
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/* pin-controller instance 0 data */
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.pin_banks = exynos5250_pin_banks0,
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.nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.weint_con = EXYNOS_WKUP_ECON_OFFSET,
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.weint_mask = EXYNOS_WKUP_EMASK_OFFSET,
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.weint_pend = EXYNOS_WKUP_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.eint_wkup_init = exynos_eint_wkup_init,
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.label = "exynos5250-gpio-ctrl0",
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}, {
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/* pin-controller instance 1 data */
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.pin_banks = exynos5250_pin_banks1,
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.nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.label = "exynos5250-gpio-ctrl1",
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}, {
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/* pin-controller instance 2 data */
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.pin_banks = exynos5250_pin_banks2,
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.nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.label = "exynos5250-gpio-ctrl2",
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}, {
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/* pin-controller instance 3 data */
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.pin_banks = exynos5250_pin_banks3,
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.nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
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.geint_con = EXYNOS_GPIO_ECON_OFFSET,
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.geint_mask = EXYNOS_GPIO_EMASK_OFFSET,
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.geint_pend = EXYNOS_GPIO_EPEND_OFFSET,
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.svc = EXYNOS_SVC_OFFSET,
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.eint_gpio_init = exynos_eint_gpio_init,
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.label = "exynos5250-gpio-ctrl3",
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},
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};
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@ -948,6 +948,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
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.data = (void *)exynos4210_pin_ctrl },
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{ .compatible = "samsung,exynos4x12-pinctrl",
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.data = (void *)exynos4x12_pin_ctrl },
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{ .compatible = "samsung,exynos5250-pinctrl",
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.data = (void *)exynos5250_pin_ctrl },
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{},
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};
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MODULE_DEVICE_TABLE(of, samsung_pinctrl_dt_match);
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@ -237,5 +237,6 @@ struct samsung_pmx_func {
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/* list of all exported SoC specific data */
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extern struct samsung_pin_ctrl exynos4210_pin_ctrl[];
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extern struct samsung_pin_ctrl exynos4x12_pin_ctrl[];
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extern struct samsung_pin_ctrl exynos5250_pin_ctrl[];
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#endif /* __PINCTRL_SAMSUNG_H */
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