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drm/i915: Handle ringbuffer stalls when flushing
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
parent
63256ec534
commit
b72f3acb71
@ -2148,8 +2148,8 @@ i915_gem_flush_ring(struct drm_device *dev,
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uint32_t invalidate_domains,
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uint32_t flush_domains)
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{
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ring->flush(ring, invalidate_domains, flush_domains);
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i915_gem_process_flushing_list(dev, flush_domains, ring);
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if (ring->flush(ring, invalidate_domains, flush_domains) == 0)
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i915_gem_process_flushing_list(dev, flush_domains, ring);
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}
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static int i915_ring_idle(struct drm_device *dev,
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@ -924,7 +924,7 @@ i915_gem_execbuffer_retire_commands(struct drm_device *dev,
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struct intel_ring_buffer *ring)
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{
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struct drm_i915_gem_request *request;
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u32 flush_domains;
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u32 invalidate;
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/*
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* Ensure that the commands in the batch buffer are
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@ -932,11 +932,13 @@ i915_gem_execbuffer_retire_commands(struct drm_device *dev,
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*
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* The sampler always gets flushed on i965 (sigh).
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*/
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flush_domains = 0;
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invalidate = I915_GEM_DOMAIN_COMMAND;
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if (INTEL_INFO(dev)->gen >= 4)
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flush_domains |= I915_GEM_DOMAIN_SAMPLER;
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ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains);
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invalidate |= I915_GEM_DOMAIN_SAMPLER;
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if (ring->flush(ring, invalidate, 0)) {
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i915_gem_next_request_seqno(dev, ring);
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return;
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}
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/* Add a breadcrumb for the completion of the batch buffer */
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request = kzalloc(sizeof(*request), GFP_KERNEL);
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@ -48,7 +48,7 @@ static u32 i915_gem_get_seqno(struct drm_device *dev)
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return seqno;
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}
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static void
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static int
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render_ring_flush(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains)
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@ -56,6 +56,7 @@ render_ring_flush(struct intel_ring_buffer *ring,
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struct drm_device *dev = ring->dev;
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 cmd;
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int ret;
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#if WATCH_EXEC
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DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
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@ -116,12 +117,16 @@ render_ring_flush(struct intel_ring_buffer *ring,
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#if WATCH_EXEC
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DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
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#endif
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if (intel_ring_begin(ring, 2) == 0) {
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intel_ring_emit(ring, cmd);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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}
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ret = intel_ring_begin(ring, 2);
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if (ret)
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return ret;
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intel_ring_emit(ring, cmd);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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}
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return 0;
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}
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static void ring_write_tail(struct intel_ring_buffer *ring,
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@ -534,19 +539,24 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
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POSTING_READ(mmio);
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}
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static void
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static int
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bsd_ring_flush(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains)
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{
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if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
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return;
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int ret;
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if (intel_ring_begin(ring, 2) == 0) {
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intel_ring_emit(ring, MI_FLUSH);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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}
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if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
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return 0;
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ret = intel_ring_begin(ring, 2);
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_FLUSH);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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return 0;
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}
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static int
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@ -980,20 +990,25 @@ static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
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GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
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}
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static void gen6_ring_flush(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains)
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static int gen6_ring_flush(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains)
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{
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if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
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return;
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int ret;
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if (intel_ring_begin(ring, 4) == 0) {
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intel_ring_emit(ring, MI_FLUSH_DW);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_advance(ring);
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}
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if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
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return 0;
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ret = intel_ring_begin(ring, 4);
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_FLUSH_DW);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_advance(ring);
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return 0;
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}
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static int
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@ -1122,20 +1137,25 @@ static int blt_ring_begin(struct intel_ring_buffer *ring,
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return intel_ring_begin(ring, 4);
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}
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static void blt_ring_flush(struct intel_ring_buffer *ring,
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static int blt_ring_flush(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains)
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{
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if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
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return;
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int ret;
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if (blt_ring_begin(ring, 4) == 0) {
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intel_ring_emit(ring, MI_FLUSH_DW);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_advance(ring);
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}
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if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
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return 0;
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ret = blt_ring_begin(ring, 4);
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if (ret)
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return ret;
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intel_ring_emit(ring, MI_FLUSH_DW);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, 0);
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intel_ring_advance(ring);
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return 0;
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}
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static void blt_ring_cleanup(struct intel_ring_buffer *ring)
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@ -63,9 +63,9 @@ struct intel_ring_buffer {
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void (*write_tail)(struct intel_ring_buffer *ring,
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u32 value);
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void (*flush)(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains);
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int __must_check (*flush)(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains);
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int (*add_request)(struct intel_ring_buffer *ring,
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u32 *seqno);
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u32 (*get_seqno)(struct intel_ring_buffer *ring);
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