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ath9k: Handle MCI_STATE_AIC_CAL_SINGLE
This patch adds routines to handle the MCI message AIC_CAL_SINGLE, starting the required HW calibration. Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
This commit is contained in:
Sujith Manoharan
Kalle Valo
parent
6dacafea2d
commit
b6ab9ae2ee
@ -30,6 +30,175 @@ static bool ar9003_hw_is_aic_enabled(struct ath_hw *ah)
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return true;
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}
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static void ar9003_aic_gain_table(struct ath_hw *ah)
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{
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u32 aic_atten_word[19], i;
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/* Config LNA gain difference */
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REG_WRITE(ah, AR_PHY_BT_COEX_4, 0x2c200a00);
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REG_WRITE(ah, AR_PHY_BT_COEX_5, 0x5c4e4438);
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/* Program gain table */
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aic_atten_word[0] = (0x1 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x0 & 0xf) << 5 |
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(0x1f & 0x1f); /* -01 dB: 4'd1, 5'd31, 00 dB: 4'd0, 5'd31 */
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aic_atten_word[1] = (0x3 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x2 & 0xf) << 5 |
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(0x1f & 0x1f); /* -03 dB: 4'd3, 5'd31, -02 dB: 4'd2, 5'd31 */
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aic_atten_word[2] = (0x5 & 0xf) << 14 | (0x1f & 0x1f) << 9 | (0x4 & 0xf) << 5 |
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(0x1f & 0x1f); /* -05 dB: 4'd5, 5'd31, -04 dB: 4'd4, 5'd31 */
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aic_atten_word[3] = (0x1 & 0xf) << 14 | (0x1e & 0x1f) << 9 | (0x0 & 0xf) << 5 |
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(0x1e & 0x1f); /* -07 dB: 4'd1, 5'd30, -06 dB: 4'd0, 5'd30 */
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aic_atten_word[4] = (0x3 & 0xf) << 14 | (0x1e & 0x1f) << 9 | (0x2 & 0xf) << 5 |
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(0x1e & 0x1f); /* -09 dB: 4'd3, 5'd30, -08 dB: 4'd2, 5'd30 */
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aic_atten_word[5] = (0x5 & 0xf) << 14 | (0x1e & 0x1f) << 9 | (0x4 & 0xf) << 5 |
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(0x1e & 0x1f); /* -11 dB: 4'd5, 5'd30, -10 dB: 4'd4, 5'd30 */
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aic_atten_word[6] = (0x1 & 0xf) << 14 | (0xf & 0x1f) << 9 | (0x0 & 0xf) << 5 |
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(0xf & 0x1f); /* -13 dB: 4'd1, 5'd15, -12 dB: 4'd0, 5'd15 */
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aic_atten_word[7] = (0x3 & 0xf) << 14 | (0xf & 0x1f) << 9 | (0x2 & 0xf) << 5 |
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(0xf & 0x1f); /* -15 dB: 4'd3, 5'd15, -14 dB: 4'd2, 5'd15 */
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aic_atten_word[8] = (0x5 & 0xf) << 14 | (0xf & 0x1f) << 9 | (0x4 & 0xf) << 5 |
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(0xf & 0x1f); /* -17 dB: 4'd5, 5'd15, -16 dB: 4'd4, 5'd15 */
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aic_atten_word[9] = (0x1 & 0xf) << 14 | (0x7 & 0x1f) << 9 | (0x0 & 0xf) << 5 |
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(0x7 & 0x1f); /* -19 dB: 4'd1, 5'd07, -18 dB: 4'd0, 5'd07 */
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aic_atten_word[10] = (0x3 & 0xf) << 14 | (0x7 & 0x1f) << 9 | (0x2 & 0xf) << 5 |
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(0x7 & 0x1f); /* -21 dB: 4'd3, 5'd07, -20 dB: 4'd2, 5'd07 */
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aic_atten_word[11] = (0x5 & 0xf) << 14 | (0x7 & 0x1f) << 9 | (0x4 & 0xf) << 5 |
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(0x7 & 0x1f); /* -23 dB: 4'd5, 5'd07, -22 dB: 4'd4, 5'd07 */
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aic_atten_word[12] = (0x7 & 0xf) << 14 | (0x7 & 0x1f) << 9 | (0x6 & 0xf) << 5 |
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(0x7 & 0x1f); /* -25 dB: 4'd7, 5'd07, -24 dB: 4'd6, 5'd07 */
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aic_atten_word[13] = (0x3 & 0xf) << 14 | (0x3 & 0x1f) << 9 | (0x2 & 0xf) << 5 |
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(0x3 & 0x1f); /* -27 dB: 4'd3, 5'd03, -26 dB: 4'd2, 5'd03 */
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aic_atten_word[14] = (0x5 & 0xf) << 14 | (0x3 & 0x1f) << 9 | (0x4 & 0xf) << 5 |
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(0x3 & 0x1f); /* -29 dB: 4'd5, 5'd03, -28 dB: 4'd4, 5'd03 */
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aic_atten_word[15] = (0x1 & 0xf) << 14 | (0x1 & 0x1f) << 9 | (0x0 & 0xf) << 5 |
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(0x1 & 0x1f); /* -31 dB: 4'd1, 5'd01, -30 dB: 4'd0, 5'd01 */
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aic_atten_word[16] = (0x3 & 0xf) << 14 | (0x1 & 0x1f) << 9 | (0x2 & 0xf) << 5 |
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(0x1 & 0x1f); /* -33 dB: 4'd3, 5'd01, -32 dB: 4'd2, 5'd01 */
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aic_atten_word[17] = (0x5 & 0xf) << 14 | (0x1 & 0x1f) << 9 | (0x4 & 0xf) << 5 |
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(0x1 & 0x1f); /* -35 dB: 4'd5, 5'd01, -34 dB: 4'd4, 5'd01 */
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aic_atten_word[18] = (0x7 & 0xf) << 14 | (0x1 & 0x1f) << 9 | (0x6 & 0xf) << 5 |
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(0x1 & 0x1f); /* -37 dB: 4'd7, 5'd01, -36 dB: 4'd6, 5'd01 */
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/* Write to Gain table with auto increment enabled. */
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REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
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(ATH_AIC_SRAM_AUTO_INCREMENT |
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ATH_AIC_SRAM_GAIN_TABLE_OFFSET));
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for (i = 0; i < 19; i++) {
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REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000),
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aic_atten_word[i]);
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}
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}
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static void ar9003_aic_cal_start(struct ath_hw *ah, u8 min_valid_count)
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{
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struct ath9k_hw_aic *aic = &ah->btcoex_hw.aic;
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int i;
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/* Write to Gain table with auto increment enabled. */
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REG_WRITE(ah, (AR_PHY_AIC_SRAM_ADDR_B0 + 0x3000),
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(ATH_AIC_SRAM_AUTO_INCREMENT |
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ATH_AIC_SRAM_CAL_OFFSET));
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for (i = 0; i < ATH_AIC_MAX_BT_CHANNEL; i++) {
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REG_WRITE(ah, (AR_PHY_AIC_SRAM_DATA_B0 + 0x3000), 0);
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aic->aic_sram[i] = 0;
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}
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REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B0,
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(SM(0, AR_PHY_AIC_MON_ENABLE) |
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SM(127, AR_PHY_AIC_CAL_MAX_HOP_COUNT) |
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SM(min_valid_count, AR_PHY_AIC_CAL_MIN_VALID_COUNT) |
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SM(37, AR_PHY_AIC_F_WLAN) |
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SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) |
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SM(0, AR_PHY_AIC_CAL_ENABLE) |
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SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) |
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SM(0, AR_PHY_AIC_ENABLE)));
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REG_WRITE(ah, AR_PHY_AIC_CTRL_0_B1,
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(SM(0, AR_PHY_AIC_MON_ENABLE) |
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SM(1, AR_PHY_AIC_CAL_CH_VALID_RESET) |
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SM(0, AR_PHY_AIC_CAL_ENABLE) |
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SM(0x40, AR_PHY_AIC_BTTX_PWR_THR) |
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SM(0, AR_PHY_AIC_ENABLE)));
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REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B0,
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(SM(8, AR_PHY_AIC_CAL_BT_REF_DELAY) |
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SM(0, AR_PHY_AIC_BT_IDLE_CFG) |
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SM(1, AR_PHY_AIC_STDBY_COND) |
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SM(37, AR_PHY_AIC_STDBY_ROT_ATT_DB) |
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SM(5, AR_PHY_AIC_STDBY_COM_ATT_DB) |
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SM(15, AR_PHY_AIC_RSSI_MAX) |
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SM(0, AR_PHY_AIC_RSSI_MIN)));
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REG_WRITE(ah, AR_PHY_AIC_CTRL_1_B1,
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(SM(15, AR_PHY_AIC_RSSI_MAX) |
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SM(0, AR_PHY_AIC_RSSI_MIN)));
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REG_WRITE(ah, AR_PHY_AIC_CTRL_2_B0,
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(SM(44, AR_PHY_AIC_RADIO_DELAY) |
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SM(8, AR_PHY_AIC_CAL_STEP_SIZE_CORR) |
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SM(12, AR_PHY_AIC_CAL_ROT_IDX_CORR) |
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SM(2, AR_PHY_AIC_CAL_CONV_CHECK_FACTOR) |
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SM(5, AR_PHY_AIC_ROT_IDX_COUNT_MAX) |
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SM(0, AR_PHY_AIC_CAL_SYNTH_TOGGLE) |
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SM(0, AR_PHY_AIC_CAL_SYNTH_AFTER_BTRX) |
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SM(200, AR_PHY_AIC_CAL_SYNTH_SETTLING)));
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REG_WRITE(ah, AR_PHY_AIC_CTRL_3_B0,
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(SM(2, AR_PHY_AIC_MON_MAX_HOP_COUNT) |
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SM(1, AR_PHY_AIC_MON_MIN_STALE_COUNT) |
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SM(1, AR_PHY_AIC_MON_PWR_EST_LONG) |
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SM(2, AR_PHY_AIC_MON_PD_TALLY_SCALING) |
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SM(10, AR_PHY_AIC_MON_PERF_THR) |
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SM(2, AR_PHY_AIC_CAL_TARGET_MAG_SETTING) |
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SM(1, AR_PHY_AIC_CAL_PERF_CHECK_FACTOR) |
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SM(1, AR_PHY_AIC_CAL_PWR_EST_LONG)));
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REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B0,
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(SM(2, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) |
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SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) |
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SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) |
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SM(2, AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF) |
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SM(1, AR_PHY_AIC_CAL_COM_ATT_DB_FIXED)));
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REG_WRITE(ah, AR_PHY_AIC_CTRL_4_B1,
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(SM(2, AR_PHY_AIC_CAL_ROT_ATT_DB_EST_ISO) |
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SM(3, AR_PHY_AIC_CAL_COM_ATT_DB_EST_ISO) |
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SM(0, AR_PHY_AIC_CAL_ISO_EST_INIT_SETTING) |
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SM(2, AR_PHY_AIC_CAL_COM_ATT_DB_BACKOFF) |
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SM(1, AR_PHY_AIC_CAL_COM_ATT_DB_FIXED)));
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ar9003_aic_gain_table(ah);
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/* Need to enable AIC reference signal in BT modem. */
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REG_WRITE(ah, ATH_AIC_BT_JUPITER_CTRL,
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(REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) |
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ATH_AIC_BT_AIC_ENABLE));
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aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32);
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/* Start calibration */
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REG_CLR_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
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REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_CH_VALID_RESET);
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REG_SET_BIT(ah, AR_PHY_AIC_CTRL_0_B1, AR_PHY_AIC_CAL_ENABLE);
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aic->aic_caled_chan = 0;
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aic->aic_cal_state = AIC_CAL_STATE_STARTED;
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}
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u8 ar9003_aic_calibration_single(struct ath_hw *ah)
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{
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struct ath9k_hw_mci *mci_hw = &ah->btcoex_hw.mci;
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u8 cal_ret = 0;
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int num_chan;
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num_chan = MS(mci_hw->config, ATH_MCI_CONFIG_AIC_CAL_NUM_CHAN);
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ar9003_aic_cal_start(ah, num_chan);
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return cal_ret;
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}
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void ar9003_hw_attach_aic_ops(struct ath_hw *ah)
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{
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struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
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@ -31,6 +31,13 @@
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#define ATH_AIC_BT_JUPITER_CTRL 0x66820
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#define ATH_AIC_BT_AIC_ENABLE 0x02
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enum aic_cal_state {
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AIC_CAL_STATE_IDLE = 0,
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AIC_CAL_STATE_STARTED,
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AIC_CAL_STATE_DONE,
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AIC_CAL_STATE_ERROR
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};
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struct ath_aic_sram_info {
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bool valid:1;
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bool vga_quad_sign:1;
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@ -46,4 +53,6 @@ struct ath_aic_out_info {
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struct ath_aic_sram_info sram;
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};
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u8 ar9003_aic_calibration_single(struct ath_hw *ah);
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#endif /* AR9003_AIC_H */
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@ -19,6 +19,7 @@
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#include "hw-ops.h"
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#include "ar9003_phy.h"
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#include "ar9003_mci.h"
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#include "ar9003_aic.h"
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static void ar9003_mci_reset_req_wakeup(struct ath_hw *ah)
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{
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@ -1362,6 +1363,9 @@ u32 ar9003_mci_state(struct ath_hw *ah, u32 state_type)
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value = (!mci->unhalt_bt_gpm && mci->need_flush_btinfo) ? 1 : 0;
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mci->need_flush_btinfo = false;
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break;
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case MCI_STATE_AIC_CAL_SINGLE:
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value = ar9003_aic_calibration_single(ah);
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break;
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default:
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break;
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}
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@ -107,6 +107,7 @@ struct ath9k_hw_aic {
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struct ath_btcoex_hw {
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enum ath_btcoex_scheme scheme;
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struct ath9k_hw_mci mci;
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struct ath9k_hw_aic aic;
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bool enabled;
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u8 wlanactive_gpio;
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u8 btactive_gpio;
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