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Merge branch 'txgbe-phylink-support'
Jiawen Wu says: ==================== TXGBE PHYLINK support Implement I2C, SFP, GPIO and PHYLINK to setup TXGBE link. Because our I2C and PCS are based on Synopsys Designware IP-core, extend the i2c-designware and pcs-xpcs driver to realize our functions. ==================== Link: https://lore.kernel.org/r/20230606092107.764621-1-jiawenwu@trustnetic.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Paolo Abeni
commit
b62d9e2004
@ -40,6 +40,16 @@ config NGBE
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config TXGBE
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tristate "Wangxun(R) 10GbE PCI Express adapters support"
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depends on PCI
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depends on COMMON_CLK
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select REGMAP
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select I2C
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select I2C_DESIGNWARE_PLATFORM
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select PHYLINK
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select HWMON if TXGBE=y
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select SFP
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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select PCS_XPCS
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select LIBWX
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help
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This driver supports Wangxun(R) 10GbE PCI Express family of
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@ -2048,7 +2048,8 @@ void wx_free_irq(struct wx *wx)
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free_irq(entry->vector, q_vector);
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}
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free_irq(wx->msix_entries[vector].vector, wx);
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if (wx->mac.type == wx_mac_em)
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free_irq(wx->msix_entries[vector].vector, wx);
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}
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EXPORT_SYMBOL(wx_free_irq);
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@ -83,7 +83,9 @@
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#define WX_GPIO_INTMASK 0x14834
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#define WX_GPIO_INTTYPE_LEVEL 0x14838
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#define WX_GPIO_POLARITY 0x1483C
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#define WX_GPIO_INTSTATUS 0x14844
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#define WX_GPIO_EOI 0x1484C
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#define WX_GPIO_EXT 0x14850
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/*********************** Transmit DMA registers **************************/
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/* transmit global control */
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@ -814,6 +816,7 @@ enum wx_isb_idx {
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struct wx {
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unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
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void *priv;
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u8 __iomem *hw_addr;
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struct pci_dev *pdev;
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struct net_device *netdev;
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@ -846,6 +849,7 @@ struct wx {
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bool wol_enabled;
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bool ncsi_enabled;
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bool gpio_ctrl;
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raw_spinlock_t gpio_lock;
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/* Tx fast path data */
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int num_tx_queues;
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@ -8,4 +8,5 @@ obj-$(CONFIG_TXGBE) += txgbe.o
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txgbe-objs := txgbe_main.o \
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txgbe_hw.o \
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txgbe_phy.o \
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txgbe_ethtool.o
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@ -6,11 +6,39 @@
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#include <linux/netdevice.h>
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#include "../libwx/wx_ethtool.h"
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#include "../libwx/wx_type.h"
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#include "txgbe_type.h"
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#include "txgbe_ethtool.h"
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static int txgbe_nway_reset(struct net_device *netdev)
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{
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struct txgbe *txgbe = netdev_to_txgbe(netdev);
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return phylink_ethtool_nway_reset(txgbe->phylink);
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}
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static int txgbe_get_link_ksettings(struct net_device *netdev,
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struct ethtool_link_ksettings *cmd)
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{
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struct txgbe *txgbe = netdev_to_txgbe(netdev);
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return phylink_ethtool_ksettings_get(txgbe->phylink, cmd);
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}
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static int txgbe_set_link_ksettings(struct net_device *netdev,
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const struct ethtool_link_ksettings *cmd)
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{
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struct txgbe *txgbe = netdev_to_txgbe(netdev);
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return phylink_ethtool_ksettings_set(txgbe->phylink, cmd);
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}
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static const struct ethtool_ops txgbe_ethtool_ops = {
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.get_drvinfo = wx_get_drvinfo,
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.nway_reset = txgbe_nway_reset,
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.get_link = ethtool_op_get_link,
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.get_link_ksettings = txgbe_get_link_ksettings,
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.set_link_ksettings = txgbe_set_link_ksettings,
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};
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void txgbe_set_ethtool_ops(struct net_device *netdev)
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@ -7,6 +7,7 @@
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#include <linux/netdevice.h>
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#include <linux/string.h>
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#include <linux/etherdevice.h>
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#include <linux/phylink.h>
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#include <net/ip.h>
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#include <linux/if_vlan.h>
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@ -15,6 +16,7 @@
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#include "../libwx/wx_hw.h"
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#include "txgbe_type.h"
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#include "txgbe_hw.h"
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#include "txgbe_phy.h"
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#include "txgbe_ethtool.h"
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char txgbe_driver_name[] = "txgbe";
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@ -81,6 +83,8 @@ static int txgbe_enumerate_functions(struct wx *wx)
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**/
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static void txgbe_irq_enable(struct wx *wx, bool queues)
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{
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wr32(wx, WX_PX_MISC_IEN, TXGBE_PX_MISC_IEN_MASK);
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/* unmask interrupt */
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wx_intr_enable(wx, TXGBE_INTR_MISC(wx));
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if (queues)
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@ -128,17 +132,6 @@ static irqreturn_t txgbe_intr(int __always_unused irq, void *data)
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return IRQ_HANDLED;
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}
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static irqreturn_t txgbe_msix_other(int __always_unused irq, void *data)
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{
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struct wx *wx = data;
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/* re-enable the original interrupt state */
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if (netif_running(wx->netdev))
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txgbe_irq_enable(wx, false);
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return IRQ_HANDLED;
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}
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/**
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* txgbe_request_msix_irqs - Initialize MSI-X interrupts
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* @wx: board private structure
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@ -170,13 +163,6 @@ static int txgbe_request_msix_irqs(struct wx *wx)
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}
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}
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err = request_irq(wx->msix_entries[vector].vector,
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txgbe_msix_other, 0, netdev->name, wx);
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if (err) {
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wx_err(wx, "request_irq for msix_other failed: %d\n", err);
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goto free_queue_irqs;
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}
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return 0;
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free_queue_irqs:
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@ -219,7 +205,8 @@ static int txgbe_request_irq(struct wx *wx)
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static void txgbe_up_complete(struct wx *wx)
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{
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u32 reg;
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struct net_device *netdev = wx->netdev;
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struct txgbe *txgbe;
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wx_control_hw(wx, true);
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wx_configure_vectors(wx);
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@ -228,24 +215,17 @@ static void txgbe_up_complete(struct wx *wx)
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smp_mb__before_atomic();
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wx_napi_enable_all(wx);
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txgbe = netdev_to_txgbe(netdev);
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phylink_start(txgbe->phylink);
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/* clear any pending interrupts, may auto mask */
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rd32(wx, WX_PX_IC(0));
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rd32(wx, WX_PX_IC(1));
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rd32(wx, WX_PX_MISC_IC);
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txgbe_irq_enable(wx, true);
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/* Configure MAC Rx and Tx when link is up */
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reg = rd32(wx, WX_MAC_RX_CFG);
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wr32(wx, WX_MAC_RX_CFG, reg);
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wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
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reg = rd32(wx, WX_MAC_WDG_TIMEOUT);
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wr32(wx, WX_MAC_WDG_TIMEOUT, reg);
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reg = rd32(wx, WX_MAC_TX_CFG);
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wr32(wx, WX_MAC_TX_CFG, (reg & ~WX_MAC_TX_CFG_SPEED_MASK) | WX_MAC_TX_CFG_SPEED_10G);
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/* enable transmits */
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netif_tx_start_all_queues(wx->netdev);
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netif_carrier_on(wx->netdev);
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netif_tx_start_all_queues(netdev);
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}
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static void txgbe_reset(struct wx *wx)
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@ -280,7 +260,6 @@ static void txgbe_disable_device(struct wx *wx)
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wx_disable_rx_queue(wx, wx->rx_ring[i]);
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netif_tx_stop_all_queues(netdev);
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netif_carrier_off(netdev);
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netif_tx_disable(netdev);
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wx_irq_disable(wx);
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@ -311,8 +290,11 @@ static void txgbe_disable_device(struct wx *wx)
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static void txgbe_down(struct wx *wx)
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{
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struct txgbe *txgbe = netdev_to_txgbe(wx->netdev);
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txgbe_disable_device(wx);
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txgbe_reset(wx);
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phylink_stop(txgbe->phylink);
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wx_clean_all_tx_rings(wx);
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wx_clean_all_rx_rings(wx);
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@ -516,6 +498,7 @@ static int txgbe_probe(struct pci_dev *pdev,
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struct net_device *netdev;
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int err, expected_gts;
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struct wx *wx = NULL;
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struct txgbe *txgbe;
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u16 eeprom_verh = 0, eeprom_verl = 0, offset = 0;
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u16 eeprom_cfg_blkh = 0, eeprom_cfg_blkl = 0;
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@ -680,10 +663,23 @@ static int txgbe_probe(struct pci_dev *pdev,
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"0x%08x", etrack_id);
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}
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err = register_netdev(netdev);
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txgbe = devm_kzalloc(&pdev->dev, sizeof(*txgbe), GFP_KERNEL);
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if (!txgbe) {
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err = -ENOMEM;
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goto err_release_hw;
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}
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txgbe->wx = wx;
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wx->priv = txgbe;
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err = txgbe_init_phy(txgbe);
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if (err)
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goto err_release_hw;
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err = register_netdev(netdev);
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if (err)
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goto err_remove_phy;
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pci_set_drvdata(pdev, wx);
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netif_tx_stop_all_queues(netdev);
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@ -711,6 +707,8 @@ static int txgbe_probe(struct pci_dev *pdev,
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return 0;
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err_remove_phy:
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txgbe_remove_phy(txgbe);
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err_release_hw:
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wx_clear_interrupt_scheme(wx);
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wx_control_hw(wx, false);
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@ -736,11 +734,14 @@ err_pci_disable_dev:
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static void txgbe_remove(struct pci_dev *pdev)
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{
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struct wx *wx = pci_get_drvdata(pdev);
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struct txgbe *txgbe = wx->priv;
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struct net_device *netdev;
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netdev = wx->netdev;
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unregister_netdev(netdev);
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txgbe_remove_phy(txgbe);
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pci_release_selected_regions(pdev,
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pci_select_bars(pdev, IORESOURCE_MEM));
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673
drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c
Normal file
673
drivers/net/ethernet/wangxun/txgbe/txgbe_phy.c
Normal file
@ -0,0 +1,673 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */
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#include <linux/gpio/machine.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/property.h>
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/i2c.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/pcs/pcs-xpcs.h>
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#include <linux/phylink.h>
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#include "../libwx/wx_type.h"
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#include "../libwx/wx_lib.h"
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#include "../libwx/wx_hw.h"
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#include "txgbe_type.h"
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#include "txgbe_phy.h"
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static int txgbe_swnodes_register(struct txgbe *txgbe)
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{
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struct txgbe_nodes *nodes = &txgbe->nodes;
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struct pci_dev *pdev = txgbe->wx->pdev;
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struct software_node *swnodes;
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u32 id;
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id = (pdev->bus->number << 8) | pdev->devfn;
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snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id);
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snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id);
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snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id);
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snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id);
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swnodes = nodes->swnodes;
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/* GPIO 0: tx fault
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* GPIO 1: tx disable
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* GPIO 2: sfp module absent
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* GPIO 3: rx signal lost
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* GPIO 4: rate select, 1G(0) 10G(1)
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* GPIO 5: rate select, 1G(0) 10G(1)
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*/
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nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default");
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swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props);
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nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH);
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nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH);
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nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW);
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nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH);
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nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH);
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nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH);
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nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c");
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nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model");
|
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nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ);
|
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swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props);
|
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nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]);
|
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|
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nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp");
|
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nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref);
|
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nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref);
|
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nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref);
|
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nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref);
|
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nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref);
|
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nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref);
|
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nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref);
|
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swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props);
|
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nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]);
|
||||
|
||||
nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status");
|
||||
nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref);
|
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swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props);
|
||||
|
||||
nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO];
|
||||
nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C];
|
||||
nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP];
|
||||
nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK];
|
||||
|
||||
return software_node_register_node_group(nodes->group);
|
||||
}
|
||||
|
||||
static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum)
|
||||
{
|
||||
struct wx *wx = bus->priv;
|
||||
u32 offset, val;
|
||||
|
||||
if (addr)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
offset = devnum << 16 | regnum;
|
||||
|
||||
/* Set the LAN port indicator to IDA_ADDR */
|
||||
wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
|
||||
|
||||
/* Read the data from IDA_DATA register */
|
||||
val = rd32(wx, TXGBE_XPCS_IDA_DATA);
|
||||
|
||||
return (u16)val;
|
||||
}
|
||||
|
||||
static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val)
|
||||
{
|
||||
struct wx *wx = bus->priv;
|
||||
u32 offset;
|
||||
|
||||
if (addr)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
offset = devnum << 16 | regnum;
|
||||
|
||||
/* Set the LAN port indicator to IDA_ADDR */
|
||||
wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
|
||||
|
||||
/* Write the data to IDA_DATA register */
|
||||
wr32(wx, TXGBE_XPCS_IDA_DATA, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int txgbe_mdio_pcs_init(struct txgbe *txgbe)
|
||||
{
|
||||
struct mii_bus *mii_bus;
|
||||
struct dw_xpcs *xpcs;
|
||||
struct pci_dev *pdev;
|
||||
struct wx *wx;
|
||||
int ret = 0;
|
||||
|
||||
wx = txgbe->wx;
|
||||
pdev = wx->pdev;
|
||||
|
||||
mii_bus = devm_mdiobus_alloc(&pdev->dev);
|
||||
if (!mii_bus)
|
||||
return -ENOMEM;
|
||||
|
||||
mii_bus->name = "txgbe_pcs_mdio_bus";
|
||||
mii_bus->read_c45 = &txgbe_pcs_read;
|
||||
mii_bus->write_c45 = &txgbe_pcs_write;
|
||||
mii_bus->parent = &pdev->dev;
|
||||
mii_bus->phy_mask = ~0;
|
||||
mii_bus->priv = wx;
|
||||
snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x",
|
||||
(pdev->bus->number << 8) | pdev->devfn);
|
||||
|
||||
ret = devm_mdiobus_register(&pdev->dev, mii_bus);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
xpcs = xpcs_create_mdiodev(mii_bus, 0, PHY_INTERFACE_MODE_10GBASER);
|
||||
if (IS_ERR(xpcs))
|
||||
return PTR_ERR(xpcs);
|
||||
|
||||
txgbe->xpcs = xpcs;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config,
|
||||
phy_interface_t interface)
|
||||
{
|
||||
struct txgbe *txgbe = netdev_to_txgbe(to_net_dev(config->dev));
|
||||
|
||||
return &txgbe->xpcs->pcs;
|
||||
}
|
||||
|
||||
static void txgbe_mac_config(struct phylink_config *config, unsigned int mode,
|
||||
const struct phylink_link_state *state)
|
||||
{
|
||||
}
|
||||
|
||||
static void txgbe_mac_link_down(struct phylink_config *config,
|
||||
unsigned int mode, phy_interface_t interface)
|
||||
{
|
||||
struct wx *wx = netdev_priv(to_net_dev(config->dev));
|
||||
|
||||
wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
|
||||
}
|
||||
|
||||
static void txgbe_mac_link_up(struct phylink_config *config,
|
||||
struct phy_device *phy,
|
||||
unsigned int mode, phy_interface_t interface,
|
||||
int speed, int duplex,
|
||||
bool tx_pause, bool rx_pause)
|
||||
{
|
||||
struct wx *wx = netdev_priv(to_net_dev(config->dev));
|
||||
u32 txcfg, wdg;
|
||||
|
||||
txcfg = rd32(wx, WX_MAC_TX_CFG);
|
||||
txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK;
|
||||
|
||||
switch (speed) {
|
||||
case SPEED_10000:
|
||||
txcfg |= WX_MAC_TX_CFG_SPEED_10G;
|
||||
break;
|
||||
case SPEED_1000:
|
||||
case SPEED_100:
|
||||
case SPEED_10:
|
||||
txcfg |= WX_MAC_TX_CFG_SPEED_1G;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE);
|
||||
|
||||
/* Re configure MAC Rx */
|
||||
wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
|
||||
wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
|
||||
wdg = rd32(wx, WX_MAC_WDG_TIMEOUT);
|
||||
wr32(wx, WX_MAC_WDG_TIMEOUT, wdg);
|
||||
}
|
||||
|
||||
static const struct phylink_mac_ops txgbe_mac_ops = {
|
||||
.mac_select_pcs = txgbe_phylink_mac_select,
|
||||
.mac_config = txgbe_mac_config,
|
||||
.mac_link_down = txgbe_mac_link_down,
|
||||
.mac_link_up = txgbe_mac_link_up,
|
||||
};
|
||||
|
||||
static int txgbe_phylink_init(struct txgbe *txgbe)
|
||||
{
|
||||
struct phylink_config *config;
|
||||
struct fwnode_handle *fwnode;
|
||||
struct wx *wx = txgbe->wx;
|
||||
phy_interface_t phy_mode;
|
||||
struct phylink *phylink;
|
||||
|
||||
config = devm_kzalloc(&wx->pdev->dev, sizeof(*config), GFP_KERNEL);
|
||||
if (!config)
|
||||
return -ENOMEM;
|
||||
|
||||
config->dev = &wx->netdev->dev;
|
||||
config->type = PHYLINK_NETDEV;
|
||||
config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
|
||||
phy_mode = PHY_INTERFACE_MODE_10GBASER;
|
||||
__set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);
|
||||
fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]);
|
||||
phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops);
|
||||
if (IS_ERR(phylink))
|
||||
return PTR_ERR(phylink);
|
||||
|
||||
txgbe->phylink = phylink;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct wx *wx = gpiochip_get_data(chip);
|
||||
int val;
|
||||
|
||||
val = rd32m(wx, WX_GPIO_EXT, BIT(offset));
|
||||
|
||||
return !!(val & BIT(offset));
|
||||
}
|
||||
|
||||
static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct wx *wx = gpiochip_get_data(chip);
|
||||
u32 val;
|
||||
|
||||
val = rd32(wx, WX_GPIO_DDR);
|
||||
if (BIT(offset) & val)
|
||||
return GPIO_LINE_DIRECTION_OUT;
|
||||
|
||||
return GPIO_LINE_DIRECTION_IN;
|
||||
}
|
||||
|
||||
static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset)
|
||||
{
|
||||
struct wx *wx = gpiochip_get_data(chip);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&wx->gpio_lock, flags);
|
||||
wr32m(wx, WX_GPIO_DDR, BIT(offset), 0);
|
||||
raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,
|
||||
int val)
|
||||
{
|
||||
struct wx *wx = gpiochip_get_data(chip);
|
||||
unsigned long flags;
|
||||
u32 set;
|
||||
|
||||
set = val ? BIT(offset) : 0;
|
||||
|
||||
raw_spin_lock_irqsave(&wx->gpio_lock, flags);
|
||||
wr32m(wx, WX_GPIO_DR, BIT(offset), set);
|
||||
wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset));
|
||||
raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void txgbe_gpio_irq_ack(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
struct wx *wx = gpiochip_get_data(gc);
|
||||
unsigned long flags;
|
||||
|
||||
raw_spin_lock_irqsave(&wx->gpio_lock, flags);
|
||||
wr32(wx, WX_GPIO_EOI, BIT(hwirq));
|
||||
raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
|
||||
}
|
||||
|
||||
static void txgbe_gpio_irq_mask(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
struct wx *wx = gpiochip_get_data(gc);
|
||||
unsigned long flags;
|
||||
|
||||
gpiochip_disable_irq(gc, hwirq);
|
||||
|
||||
raw_spin_lock_irqsave(&wx->gpio_lock, flags);
|
||||
wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), BIT(hwirq));
|
||||
raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
|
||||
}
|
||||
|
||||
static void txgbe_gpio_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
struct wx *wx = gpiochip_get_data(gc);
|
||||
unsigned long flags;
|
||||
|
||||
gpiochip_enable_irq(gc, hwirq);
|
||||
|
||||
raw_spin_lock_irqsave(&wx->gpio_lock, flags);
|
||||
wr32m(wx, WX_GPIO_INTMASK, BIT(hwirq), 0);
|
||||
raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
|
||||
}
|
||||
|
||||
static void txgbe_toggle_trigger(struct gpio_chip *gc, unsigned int offset)
|
||||
{
|
||||
struct wx *wx = gpiochip_get_data(gc);
|
||||
u32 pol, val;
|
||||
|
||||
pol = rd32(wx, WX_GPIO_POLARITY);
|
||||
val = rd32(wx, WX_GPIO_EXT);
|
||||
|
||||
if (val & BIT(offset))
|
||||
pol &= ~BIT(offset);
|
||||
else
|
||||
pol |= BIT(offset);
|
||||
|
||||
wr32(wx, WX_GPIO_POLARITY, pol);
|
||||
}
|
||||
|
||||
static int txgbe_gpio_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
struct wx *wx = gpiochip_get_data(gc);
|
||||
u32 level, polarity, mask;
|
||||
unsigned long flags;
|
||||
|
||||
mask = BIT(hwirq);
|
||||
|
||||
if (type & IRQ_TYPE_LEVEL_MASK) {
|
||||
level = 0;
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
} else {
|
||||
level = mask;
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
}
|
||||
|
||||
if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
|
||||
polarity = mask;
|
||||
else
|
||||
polarity = 0;
|
||||
|
||||
raw_spin_lock_irqsave(&wx->gpio_lock, flags);
|
||||
|
||||
wr32m(wx, WX_GPIO_INTEN, mask, mask);
|
||||
wr32m(wx, WX_GPIO_INTTYPE_LEVEL, mask, level);
|
||||
if (type == IRQ_TYPE_EDGE_BOTH)
|
||||
txgbe_toggle_trigger(gc, hwirq);
|
||||
else
|
||||
wr32m(wx, WX_GPIO_POLARITY, mask, polarity);
|
||||
|
||||
raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_chip txgbe_gpio_irq_chip = {
|
||||
.name = "txgbe_gpio_irq",
|
||||
.irq_ack = txgbe_gpio_irq_ack,
|
||||
.irq_mask = txgbe_gpio_irq_mask,
|
||||
.irq_unmask = txgbe_gpio_irq_unmask,
|
||||
.irq_set_type = txgbe_gpio_set_type,
|
||||
.flags = IRQCHIP_IMMUTABLE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static void txgbe_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
struct wx *wx = irq_desc_get_handler_data(desc);
|
||||
struct txgbe *txgbe = wx->priv;
|
||||
irq_hw_number_t hwirq;
|
||||
unsigned long gpioirq;
|
||||
struct gpio_chip *gc;
|
||||
unsigned long flags;
|
||||
u32 eicr;
|
||||
|
||||
eicr = wx_misc_isb(wx, WX_ISB_MISC);
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
gpioirq = rd32(wx, WX_GPIO_INTSTATUS);
|
||||
|
||||
gc = txgbe->gpio;
|
||||
for_each_set_bit(hwirq, &gpioirq, gc->ngpio) {
|
||||
int gpio = irq_find_mapping(gc->irq.domain, hwirq);
|
||||
u32 irq_type = irq_get_trigger_type(gpio);
|
||||
|
||||
generic_handle_domain_irq(gc->irq.domain, hwirq);
|
||||
|
||||
if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
|
||||
raw_spin_lock_irqsave(&wx->gpio_lock, flags);
|
||||
txgbe_toggle_trigger(gc, hwirq);
|
||||
raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
|
||||
}
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
|
||||
if (eicr & (TXGBE_PX_MISC_ETH_LK | TXGBE_PX_MISC_ETH_LKDN)) {
|
||||
u32 reg = rd32(wx, TXGBE_CFG_PORT_ST);
|
||||
|
||||
phylink_mac_change(txgbe->phylink, !!(reg & TXGBE_CFG_PORT_ST_LINK_UP));
|
||||
}
|
||||
|
||||
/* unmask interrupt */
|
||||
wx_intr_enable(wx, TXGBE_INTR_MISC(wx));
|
||||
}
|
||||
|
||||
static int txgbe_gpio_init(struct txgbe *txgbe)
|
||||
{
|
||||
struct gpio_irq_chip *girq;
|
||||
struct gpio_chip *gc;
|
||||
struct device *dev;
|
||||
struct wx *wx;
|
||||
int ret;
|
||||
|
||||
wx = txgbe->wx;
|
||||
dev = &wx->pdev->dev;
|
||||
|
||||
raw_spin_lock_init(&wx->gpio_lock);
|
||||
|
||||
gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
|
||||
if (!gc)
|
||||
return -ENOMEM;
|
||||
|
||||
gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x",
|
||||
(wx->pdev->bus->number << 8) | wx->pdev->devfn);
|
||||
if (!gc->label)
|
||||
return -ENOMEM;
|
||||
|
||||
gc->base = -1;
|
||||
gc->ngpio = 6;
|
||||
gc->owner = THIS_MODULE;
|
||||
gc->parent = dev;
|
||||
gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]);
|
||||
gc->get = txgbe_gpio_get;
|
||||
gc->get_direction = txgbe_gpio_get_direction;
|
||||
gc->direction_input = txgbe_gpio_direction_in;
|
||||
gc->direction_output = txgbe_gpio_direction_out;
|
||||
|
||||
girq = &gc->irq;
|
||||
gpio_irq_chip_set_chip(girq, &txgbe_gpio_irq_chip);
|
||||
girq->parent_handler = txgbe_irq_handler;
|
||||
girq->parent_handler_data = wx;
|
||||
girq->num_parents = 1;
|
||||
girq->parents = devm_kcalloc(dev, girq->num_parents,
|
||||
sizeof(*girq->parents), GFP_KERNEL);
|
||||
if (!girq->parents)
|
||||
return -ENOMEM;
|
||||
girq->parents[0] = wx->msix_entries[wx->num_q_vectors].vector;
|
||||
girq->default_type = IRQ_TYPE_NONE;
|
||||
girq->handler = handle_bad_irq;
|
||||
|
||||
ret = devm_gpiochip_add_data(dev, gc, wx);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
txgbe->gpio = gc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int txgbe_clock_register(struct txgbe *txgbe)
|
||||
{
|
||||
struct pci_dev *pdev = txgbe->wx->pdev;
|
||||
struct clk_lookup *clock;
|
||||
char clk_name[32];
|
||||
struct clk *clk;
|
||||
|
||||
snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d",
|
||||
(pdev->bus->number << 8) | pdev->devfn);
|
||||
|
||||
clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000);
|
||||
if (IS_ERR(clk))
|
||||
return PTR_ERR(clk);
|
||||
|
||||
clock = clkdev_create(clk, NULL, clk_name);
|
||||
if (!clock) {
|
||||
clk_unregister(clk);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
txgbe->clk = clk;
|
||||
txgbe->clock = clock;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val)
|
||||
{
|
||||
struct wx *wx = context;
|
||||
|
||||
*val = rd32(wx, reg + TXGBE_I2C_BASE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val)
|
||||
{
|
||||
struct wx *wx = context;
|
||||
|
||||
wr32(wx, reg + TXGBE_I2C_BASE, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct regmap_config i2c_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_read = txgbe_i2c_read,
|
||||
.reg_write = txgbe_i2c_write,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static int txgbe_i2c_register(struct txgbe *txgbe)
|
||||
{
|
||||
struct platform_device_info info = {};
|
||||
struct platform_device *i2c_dev;
|
||||
struct regmap *i2c_regmap;
|
||||
struct pci_dev *pdev;
|
||||
struct wx *wx;
|
||||
|
||||
wx = txgbe->wx;
|
||||
pdev = wx->pdev;
|
||||
i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config);
|
||||
if (IS_ERR(i2c_regmap)) {
|
||||
wx_err(wx, "failed to init I2C regmap\n");
|
||||
return PTR_ERR(i2c_regmap);
|
||||
}
|
||||
|
||||
info.parent = &pdev->dev;
|
||||
info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]);
|
||||
info.name = "i2c_designware";
|
||||
info.id = (pdev->bus->number << 8) | pdev->devfn;
|
||||
|
||||
info.res = &DEFINE_RES_IRQ(pdev->irq);
|
||||
info.num_res = 1;
|
||||
i2c_dev = platform_device_register_full(&info);
|
||||
if (IS_ERR(i2c_dev))
|
||||
return PTR_ERR(i2c_dev);
|
||||
|
||||
txgbe->i2c_dev = i2c_dev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int txgbe_sfp_register(struct txgbe *txgbe)
|
||||
{
|
||||
struct pci_dev *pdev = txgbe->wx->pdev;
|
||||
struct platform_device_info info = {};
|
||||
struct platform_device *sfp_dev;
|
||||
|
||||
info.parent = &pdev->dev;
|
||||
info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]);
|
||||
info.name = "sfp";
|
||||
info.id = (pdev->bus->number << 8) | pdev->devfn;
|
||||
sfp_dev = platform_device_register_full(&info);
|
||||
if (IS_ERR(sfp_dev))
|
||||
return PTR_ERR(sfp_dev);
|
||||
|
||||
txgbe->sfp_dev = sfp_dev;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int txgbe_init_phy(struct txgbe *txgbe)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = txgbe_swnodes_register(txgbe);
|
||||
if (ret) {
|
||||
wx_err(txgbe->wx, "failed to register software nodes\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = txgbe_mdio_pcs_init(txgbe);
|
||||
if (ret) {
|
||||
wx_err(txgbe->wx, "failed to init mdio pcs: %d\n", ret);
|
||||
goto err_unregister_swnode;
|
||||
}
|
||||
|
||||
ret = txgbe_phylink_init(txgbe);
|
||||
if (ret) {
|
||||
wx_err(txgbe->wx, "failed to init phylink\n");
|
||||
goto err_destroy_xpcs;
|
||||
}
|
||||
|
||||
ret = txgbe_gpio_init(txgbe);
|
||||
if (ret) {
|
||||
wx_err(txgbe->wx, "failed to init gpio\n");
|
||||
goto err_destroy_phylink;
|
||||
}
|
||||
|
||||
ret = txgbe_clock_register(txgbe);
|
||||
if (ret) {
|
||||
wx_err(txgbe->wx, "failed to register clock: %d\n", ret);
|
||||
goto err_destroy_phylink;
|
||||
}
|
||||
|
||||
ret = txgbe_i2c_register(txgbe);
|
||||
if (ret) {
|
||||
wx_err(txgbe->wx, "failed to init i2c interface: %d\n", ret);
|
||||
goto err_unregister_clk;
|
||||
}
|
||||
|
||||
ret = txgbe_sfp_register(txgbe);
|
||||
if (ret) {
|
||||
wx_err(txgbe->wx, "failed to register sfp\n");
|
||||
goto err_unregister_i2c;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_unregister_i2c:
|
||||
platform_device_unregister(txgbe->i2c_dev);
|
||||
err_unregister_clk:
|
||||
clkdev_drop(txgbe->clock);
|
||||
clk_unregister(txgbe->clk);
|
||||
err_destroy_phylink:
|
||||
phylink_destroy(txgbe->phylink);
|
||||
err_destroy_xpcs:
|
||||
xpcs_destroy(txgbe->xpcs);
|
||||
err_unregister_swnode:
|
||||
software_node_unregister_node_group(txgbe->nodes.group);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void txgbe_remove_phy(struct txgbe *txgbe)
|
||||
{
|
||||
platform_device_unregister(txgbe->sfp_dev);
|
||||
platform_device_unregister(txgbe->i2c_dev);
|
||||
clkdev_drop(txgbe->clock);
|
||||
clk_unregister(txgbe->clk);
|
||||
phylink_destroy(txgbe->phylink);
|
||||
xpcs_destroy(txgbe->xpcs);
|
||||
software_node_unregister_node_group(txgbe->nodes.group);
|
||||
}
|
||||
10
drivers/net/ethernet/wangxun/txgbe/txgbe_phy.h
Normal file
10
drivers/net/ethernet/wangxun/txgbe/txgbe_phy.h
Normal file
@ -0,0 +1,10 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */
|
||||
|
||||
#ifndef _TXGBE_PHY_H_
|
||||
#define _TXGBE_PHY_H_
|
||||
|
||||
int txgbe_init_phy(struct txgbe *txgbe);
|
||||
void txgbe_remove_phy(struct txgbe *txgbe);
|
||||
|
||||
#endif /* _TXGBE_NODE_H_ */
|
||||
@ -4,6 +4,8 @@
|
||||
#ifndef _TXGBE_TYPE_H_
|
||||
#define _TXGBE_TYPE_H_
|
||||
|
||||
#include <linux/property.h>
|
||||
|
||||
/* Device IDs */
|
||||
#define TXGBE_DEV_ID_SP1000 0x1001
|
||||
#define TXGBE_DEV_ID_WX1820 0x2001
|
||||
@ -53,6 +55,39 @@
|
||||
#define TXGBE_TS_CTL 0x10300
|
||||
#define TXGBE_TS_CTL_EVAL_MD BIT(31)
|
||||
|
||||
/* GPIO register bit */
|
||||
#define TXGBE_GPIOBIT_0 BIT(0) /* I:tx fault */
|
||||
#define TXGBE_GPIOBIT_1 BIT(1) /* O:tx disabled */
|
||||
#define TXGBE_GPIOBIT_2 BIT(2) /* I:sfp module absent */
|
||||
#define TXGBE_GPIOBIT_3 BIT(3) /* I:rx signal lost */
|
||||
#define TXGBE_GPIOBIT_4 BIT(4) /* O:rate select, 1G(0) 10G(1) */
|
||||
#define TXGBE_GPIOBIT_5 BIT(5) /* O:rate select, 1G(0) 10G(1) */
|
||||
|
||||
/* Extended Interrupt Enable Set */
|
||||
#define TXGBE_PX_MISC_ETH_LKDN BIT(8)
|
||||
#define TXGBE_PX_MISC_DEV_RST BIT(10)
|
||||
#define TXGBE_PX_MISC_ETH_EVENT BIT(17)
|
||||
#define TXGBE_PX_MISC_ETH_LK BIT(18)
|
||||
#define TXGBE_PX_MISC_ETH_AN BIT(19)
|
||||
#define TXGBE_PX_MISC_INT_ERR BIT(20)
|
||||
#define TXGBE_PX_MISC_GPIO BIT(26)
|
||||
#define TXGBE_PX_MISC_IEN_MASK \
|
||||
(TXGBE_PX_MISC_ETH_LKDN | TXGBE_PX_MISC_DEV_RST | \
|
||||
TXGBE_PX_MISC_ETH_EVENT | TXGBE_PX_MISC_ETH_LK | \
|
||||
TXGBE_PX_MISC_ETH_AN | TXGBE_PX_MISC_INT_ERR | \
|
||||
TXGBE_PX_MISC_GPIO)
|
||||
|
||||
/* Port cfg registers */
|
||||
#define TXGBE_CFG_PORT_ST 0x14404
|
||||
#define TXGBE_CFG_PORT_ST_LINK_UP BIT(0)
|
||||
|
||||
/* I2C registers */
|
||||
#define TXGBE_I2C_BASE 0x14900
|
||||
|
||||
/************************************** ETH PHY ******************************/
|
||||
#define TXGBE_XPCS_IDA_ADDR 0x13000
|
||||
#define TXGBE_XPCS_IDA_DATA 0x13004
|
||||
|
||||
/* Part Number String Length */
|
||||
#define TXGBE_PBANUM_LENGTH 32
|
||||
|
||||
@ -100,4 +135,58 @@
|
||||
|
||||
extern char txgbe_driver_name[];
|
||||
|
||||
static inline struct txgbe *netdev_to_txgbe(struct net_device *netdev)
|
||||
{
|
||||
struct wx *wx = netdev_priv(netdev);
|
||||
|
||||
return wx->priv;
|
||||
}
|
||||
|
||||
#define NODE_PROP(_NAME, _PROP) \
|
||||
(const struct software_node) { \
|
||||
.name = _NAME, \
|
||||
.properties = _PROP, \
|
||||
}
|
||||
|
||||
enum txgbe_swnodes {
|
||||
SWNODE_GPIO = 0,
|
||||
SWNODE_I2C,
|
||||
SWNODE_SFP,
|
||||
SWNODE_PHYLINK,
|
||||
SWNODE_MAX
|
||||
};
|
||||
|
||||
struct txgbe_nodes {
|
||||
char gpio_name[32];
|
||||
char i2c_name[32];
|
||||
char sfp_name[32];
|
||||
char phylink_name[32];
|
||||
struct property_entry gpio_props[1];
|
||||
struct property_entry i2c_props[3];
|
||||
struct property_entry sfp_props[8];
|
||||
struct property_entry phylink_props[2];
|
||||
struct software_node_ref_args i2c_ref[1];
|
||||
struct software_node_ref_args gpio0_ref[1];
|
||||
struct software_node_ref_args gpio1_ref[1];
|
||||
struct software_node_ref_args gpio2_ref[1];
|
||||
struct software_node_ref_args gpio3_ref[1];
|
||||
struct software_node_ref_args gpio4_ref[1];
|
||||
struct software_node_ref_args gpio5_ref[1];
|
||||
struct software_node_ref_args sfp_ref[1];
|
||||
struct software_node swnodes[SWNODE_MAX];
|
||||
const struct software_node *group[SWNODE_MAX + 1];
|
||||
};
|
||||
|
||||
struct txgbe {
|
||||
struct wx *wx;
|
||||
struct txgbe_nodes nodes;
|
||||
struct dw_xpcs *xpcs;
|
||||
struct phylink *phylink;
|
||||
struct platform_device *sfp_dev;
|
||||
struct platform_device *i2c_dev;
|
||||
struct clk_lookup *clock;
|
||||
struct clk *clk;
|
||||
struct gpio_chip *gpio;
|
||||
};
|
||||
|
||||
#endif /* _TXGBE_TYPE_H_ */
|
||||
|
||||
@ -64,6 +64,16 @@ static const int xpcs_xlgmii_features[] = {
|
||||
__ETHTOOL_LINK_MODE_MASK_NBITS,
|
||||
};
|
||||
|
||||
static const int xpcs_10gbaser_features[] = {
|
||||
ETHTOOL_LINK_MODE_Pause_BIT,
|
||||
ETHTOOL_LINK_MODE_Asym_Pause_BIT,
|
||||
ETHTOOL_LINK_MODE_10000baseSR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_10000baseLR_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT,
|
||||
ETHTOOL_LINK_MODE_10000baseER_Full_BIT,
|
||||
__ETHTOOL_LINK_MODE_MASK_NBITS,
|
||||
};
|
||||
|
||||
static const int xpcs_sgmii_features[] = {
|
||||
ETHTOOL_LINK_MODE_Pause_BIT,
|
||||
ETHTOOL_LINK_MODE_Asym_Pause_BIT,
|
||||
@ -106,6 +116,10 @@ static const phy_interface_t xpcs_xlgmii_interfaces[] = {
|
||||
PHY_INTERFACE_MODE_XLGMII,
|
||||
};
|
||||
|
||||
static const phy_interface_t xpcs_10gbaser_interfaces[] = {
|
||||
PHY_INTERFACE_MODE_10GBASER,
|
||||
};
|
||||
|
||||
static const phy_interface_t xpcs_sgmii_interfaces[] = {
|
||||
PHY_INTERFACE_MODE_SGMII,
|
||||
};
|
||||
@ -123,6 +137,7 @@ enum {
|
||||
DW_XPCS_USXGMII,
|
||||
DW_XPCS_10GKR,
|
||||
DW_XPCS_XLGMII,
|
||||
DW_XPCS_10GBASER,
|
||||
DW_XPCS_SGMII,
|
||||
DW_XPCS_1000BASEX,
|
||||
DW_XPCS_2500BASEX,
|
||||
@ -246,6 +261,7 @@ static int xpcs_soft_reset(struct dw_xpcs *xpcs,
|
||||
|
||||
switch (compat->an_mode) {
|
||||
case DW_AN_C73:
|
||||
case DW_10GBASER:
|
||||
dev = MDIO_MMD_PCS;
|
||||
break;
|
||||
case DW_AN_C37_SGMII:
|
||||
@ -802,6 +818,8 @@ int xpcs_do_config(struct dw_xpcs *xpcs, phy_interface_t interface,
|
||||
return -ENODEV;
|
||||
|
||||
switch (compat->an_mode) {
|
||||
case DW_10GBASER:
|
||||
break;
|
||||
case DW_AN_C73:
|
||||
if (test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)) {
|
||||
ret = xpcs_config_aneg_c73(xpcs, compat);
|
||||
@ -998,6 +1016,9 @@ static void xpcs_get_state(struct phylink_pcs *pcs,
|
||||
return;
|
||||
|
||||
switch (compat->an_mode) {
|
||||
case DW_10GBASER:
|
||||
phylink_mii_c45_pcs_get_state(xpcs->mdiodev, state);
|
||||
break;
|
||||
case DW_AN_C73:
|
||||
ret = xpcs_get_state_c73(xpcs, state, compat);
|
||||
if (ret) {
|
||||
@ -1153,6 +1174,12 @@ static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
|
||||
.num_interfaces = ARRAY_SIZE(xpcs_xlgmii_interfaces),
|
||||
.an_mode = DW_AN_C73,
|
||||
},
|
||||
[DW_XPCS_10GBASER] = {
|
||||
.supported = xpcs_10gbaser_features,
|
||||
.interface = xpcs_10gbaser_interfaces,
|
||||
.num_interfaces = ARRAY_SIZE(xpcs_10gbaser_interfaces),
|
||||
.an_mode = DW_10GBASER,
|
||||
},
|
||||
[DW_XPCS_SGMII] = {
|
||||
.supported = xpcs_sgmii_features,
|
||||
.interface = xpcs_sgmii_interfaces,
|
||||
@ -1256,6 +1283,9 @@ static struct dw_xpcs *xpcs_create(struct mdio_device *mdiodev,
|
||||
}
|
||||
|
||||
xpcs->pcs.ops = &xpcs_phylink_ops;
|
||||
if (compat->an_mode == DW_10GBASER)
|
||||
return xpcs;
|
||||
|
||||
xpcs->pcs.poll = true;
|
||||
|
||||
ret = xpcs_soft_reset(xpcs, compat);
|
||||
|
||||
@ -18,6 +18,7 @@
|
||||
#define DW_AN_C37_SGMII 2
|
||||
#define DW_2500BASEX 3
|
||||
#define DW_AN_C37_1000BASEX 4
|
||||
#define DW_10GBASER 5
|
||||
|
||||
struct xpcs_id;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user