mirror of
https://github.com/torvalds/linux.git
synced 2024-11-21 19:41:42 +00:00
Linux 6.11-rc7
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Merge v6.11-rc7 into drm-next
Thomas needs 5a498d4d06
("drm/fbdev-dma: Only install deferred I/O
if necessary") in drm-misc, so start the backmerge cascade.
Signed-off-by: Simona Vetter <simona.vetter@ffwll.ch>
This commit is contained in:
commit
b615b9c36c
5
.mailmap
5
.mailmap
@ -60,6 +60,7 @@ Amit Nischal <quic_anischal@quicinc.com> <anischal@codeaurora.org>
|
||||
Andi Kleen <ak@linux.intel.com> <ak@suse.de>
|
||||
Andi Shyti <andi@etezian.org> <andi.shyti@samsung.com>
|
||||
Andreas Herrmann <aherrman@de.ibm.com>
|
||||
Andreas Hindborg <a.hindborg@kernel.org> <a.hindborg@samsung.com>
|
||||
Andrej Shadura <andrew.shadura@collabora.co.uk>
|
||||
Andrej Shadura <andrew@shadura.me> <andrew@beldisplaytech.com>
|
||||
Andrew Morton <akpm@linux-foundation.org>
|
||||
@ -269,6 +270,7 @@ James Ketrenos <jketreno@io.(none)>
|
||||
Jan Glauber <jan.glauber@gmail.com> <jang@de.ibm.com>
|
||||
Jan Glauber <jan.glauber@gmail.com> <jang@linux.vnet.ibm.com>
|
||||
Jan Glauber <jan.glauber@gmail.com> <jglauber@cavium.com>
|
||||
Jan Kuliga <jtkuliga.kdev@gmail.com> <jankul@alatek.krakow.pl>
|
||||
Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@linux.intel.com>
|
||||
Jarkko Sakkinen <jarkko@kernel.org> <jarkko@profian.com>
|
||||
Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@tuni.fi>
|
||||
@ -354,6 +356,8 @@ Kenneth Westfield <quic_kwestfie@quicinc.com> <kwestfie@codeaurora.org>
|
||||
Kiran Gunda <quic_kgunda@quicinc.com> <kgunda@codeaurora.org>
|
||||
Kirill Tkhai <tkhai@ya.ru> <ktkhai@virtuozzo.com>
|
||||
Kishon Vijay Abraham I <kishon@kernel.org> <kishon@ti.com>
|
||||
Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@linaro.org>
|
||||
Konrad Dybcio <konradybcio@kernel.org> <konrad.dybcio@somainline.org>
|
||||
Konstantin Khlebnikov <koct9i@gmail.com> <khlebnikov@yandex-team.ru>
|
||||
Konstantin Khlebnikov <koct9i@gmail.com> <k.khlebnikov@samsung.com>
|
||||
Koushik <raghavendra.koushik@neterion.com>
|
||||
@ -618,6 +622,7 @@ Simon Kelley <simon@thekelleys.org.uk>
|
||||
Sricharan Ramabadhran <quic_srichara@quicinc.com> <sricharan@codeaurora.org>
|
||||
Srinivas Ramana <quic_sramana@quicinc.com> <sramana@codeaurora.org>
|
||||
Sriram R <quic_srirrama@quicinc.com> <srirrama@codeaurora.org>
|
||||
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com> <sriram.yagnaraman@est.tech>
|
||||
Stanislav Fomichev <sdf@fomichev.me> <sdf@google.com>
|
||||
Stefan Wahren <wahrenst@gmx.net> <stefan.wahren@i2se.com>
|
||||
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
|
||||
|
@ -258,24 +258,29 @@ Description: (RW) When retrieving the PHC with the PTP SYS_OFFSET_EXTENDED
|
||||
the estimated point where the FPGA latches the PHC time. This
|
||||
value may be changed by writing an unsigned integer.
|
||||
|
||||
What: /sys/class/timecard/ocpN/ttyGNSS
|
||||
What: /sys/class/timecard/ocpN/ttyGNSS2
|
||||
Date: September 2021
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: These optional attributes link to the TTY serial ports
|
||||
associated with the GNSS devices.
|
||||
What: /sys/class/timecard/ocpN/tty
|
||||
Date: August 2024
|
||||
Contact: Vadim Fedorenko <vadim.fedorenko@linux.dev>
|
||||
Description: (RO) Directory containing the sysfs nodes for TTY attributes
|
||||
|
||||
What: /sys/class/timecard/ocpN/ttyMAC
|
||||
Date: September 2021
|
||||
What: /sys/class/timecard/ocpN/tty/ttyGNSS
|
||||
What: /sys/class/timecard/ocpN/tty/ttyGNSS2
|
||||
Date: August 2024
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: This optional attribute links to the TTY serial port
|
||||
associated with the Miniature Atomic Clock.
|
||||
Description: (RO) These optional attributes contain names of the TTY serial
|
||||
ports associated with the GNSS devices.
|
||||
|
||||
What: /sys/class/timecard/ocpN/ttyNMEA
|
||||
Date: September 2021
|
||||
What: /sys/class/timecard/ocpN/tty/ttyMAC
|
||||
Date: August 2024
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: This optional attribute links to the TTY serial port
|
||||
which outputs the PHC time in NMEA ZDA format.
|
||||
Description: (RO) This optional attribute contains name of the TTY serial
|
||||
port associated with the Miniature Atomic Clock.
|
||||
|
||||
What: /sys/class/timecard/ocpN/tty/ttyNMEA
|
||||
Date: August 2024
|
||||
Contact: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
Description: (RO) This optional attribute contains name of the TTY serial
|
||||
port which outputs the PHC time in NMEA ZDA format.
|
||||
|
||||
What: /sys/class/timecard/ocpN/utc_tai_offset
|
||||
Date: September 2021
|
||||
|
@ -1717,9 +1717,10 @@ The following nested keys are defined.
|
||||
entries fault back in or are written out to disk.
|
||||
|
||||
memory.zswap.writeback
|
||||
A read-write single value file. The default value is "1". The
|
||||
initial value of the root cgroup is 1, and when a new cgroup is
|
||||
created, it inherits the current value of its parent.
|
||||
A read-write single value file. The default value is "1".
|
||||
Note that this setting is hierarchical, i.e. the writeback would be
|
||||
implicitly disabled for child cgroups if the upper hierarchy
|
||||
does so.
|
||||
|
||||
When this is set to 0, all swapping attempts to swapping devices
|
||||
are disabled. This included both zswap writebacks, and swapping due
|
||||
|
@ -134,19 +134,3 @@ RISC-V Linux Kernel SV57
|
||||
ffffffff00000000 | -4 GB | ffffffff7fffffff | 2 GB | modules, BPF
|
||||
ffffffff80000000 | -2 GB | ffffffffffffffff | 2 GB | kernel
|
||||
__________________|____________|__________________|_________|____________________________________________________________
|
||||
|
||||
|
||||
Userspace VAs
|
||||
--------------------
|
||||
To maintain compatibility with software that relies on the VA space with a
|
||||
maximum of 48 bits the kernel will, by default, return virtual addresses to
|
||||
userspace from a 48-bit range (sv48). This default behavior is achieved by
|
||||
passing 0 into the hint address parameter of mmap. On CPUs with an address space
|
||||
smaller than sv48, the CPU maximum supported address space will be the default.
|
||||
|
||||
Software can "opt-in" to receiving VAs from another VA space by providing
|
||||
a hint address to mmap. When a hint address is passed to mmap, the returned
|
||||
address will never use more bits than the hint address. For example, if a hint
|
||||
address of `1 << 40` is passed to mmap, a valid returned address will never use
|
||||
bits 41 through 63. If no mappable addresses are available in that range, mmap
|
||||
will return `MAP_FAILED`.
|
||||
|
@ -1,10 +1,10 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/display/panel/wl-355608-a8.yaml#
|
||||
$id: http://devicetree.org/schemas/display/panel/anbernic,rg35xx-plus-panel.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: WL-355608-A8 3.5" (640x480 pixels) 24-bit IPS LCD panel
|
||||
title: Anbernic RG35XX series (WL-355608-A8) 3.5" 640x480 24-bit IPS LCD panel
|
||||
|
||||
maintainers:
|
||||
- Ryan Walklin <ryan@testtoast.com>
|
||||
@ -15,7 +15,14 @@ allOf:
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: wl-355608-a8
|
||||
oneOf:
|
||||
- const: anbernic,rg35xx-plus-panel
|
||||
- items:
|
||||
- enum:
|
||||
- anbernic,rg35xx-2024-panel
|
||||
- anbernic,rg35xx-h-panel
|
||||
- anbernic,rg35xx-sp-panel
|
||||
- const: anbernic,rg35xx-plus-panel
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@ -40,7 +47,7 @@ examples:
|
||||
#size-cells = <0>;
|
||||
|
||||
panel@0 {
|
||||
compatible = "wl-355608-a8";
|
||||
compatible = "anbernic,rg35xx-plus-panel";
|
||||
reg = <0>;
|
||||
|
||||
spi-3wire;
|
@ -28,7 +28,7 @@ unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
nvmem {
|
||||
soc-nvmem {
|
||||
compatible = "xlnx,zynqmp-nvmem-fw";
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
|
@ -10,7 +10,7 @@ maintainers:
|
||||
- Fabio Estevam <festevam@gmail.com>
|
||||
|
||||
allOf:
|
||||
- $ref: usb-hcd.yaml#
|
||||
- $ref: usb-device.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
@ -36,6 +36,13 @@ required:
|
||||
- compatible
|
||||
- reg
|
||||
|
||||
patternProperties:
|
||||
"^.*@[0-9a-f]{1,2}$":
|
||||
description: The hard wired USB devices
|
||||
type: object
|
||||
$ref: /schemas/usb/usb-device.yaml
|
||||
additionalProperties: true
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
@ -629,18 +629,6 @@ The preferred style for long (multi-line) comments is:
|
||||
* with beginning and ending almost-blank lines.
|
||||
*/
|
||||
|
||||
For files in net/ and drivers/net/ the preferred style for long (multi-line)
|
||||
comments is a little different.
|
||||
|
||||
.. code-block:: c
|
||||
|
||||
/* The preferred comment style for files in net/ and drivers/net
|
||||
* looks like this.
|
||||
*
|
||||
* It is nearly the same as the generally preferred comment style,
|
||||
* but there is no initial almost-blank line.
|
||||
*/
|
||||
|
||||
It's also important to comment data, whether they are basic types or derived
|
||||
types. To this end, use just one data declaration per line (no commas for
|
||||
multiple data declarations). This leaves you room for a small comment on each
|
||||
|
@ -355,23 +355,6 @@ just do it. As a result, a sequence of smaller series gets merged quicker and
|
||||
with better review coverage. Re-posting large series also increases the mailing
|
||||
list traffic.
|
||||
|
||||
Multi-line comments
|
||||
~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Comment style convention is slightly different for networking and most of
|
||||
the tree. Instead of this::
|
||||
|
||||
/*
|
||||
* foobar blah blah blah
|
||||
* another line of text
|
||||
*/
|
||||
|
||||
it is requested that you make it look like this::
|
||||
|
||||
/* foobar blah blah blah
|
||||
* another line of text
|
||||
*/
|
||||
|
||||
Local variable ordering ("reverse xmas tree", "RCS")
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
@ -392,6 +375,22 @@ When working in existing code which uses nonstandard formatting make
|
||||
your code follow the most recent guidelines, so that eventually all code
|
||||
in the domain of netdev is in the preferred format.
|
||||
|
||||
Using device-managed and cleanup.h constructs
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Netdev remains skeptical about promises of all "auto-cleanup" APIs,
|
||||
including even ``devm_`` helpers, historically. They are not the preferred
|
||||
style of implementation, merely an acceptable one.
|
||||
|
||||
Use of ``guard()`` is discouraged within any function longer than 20 lines,
|
||||
``scoped_guard()`` is considered more readable. Using normal lock/unlock is
|
||||
still (weakly) preferred.
|
||||
|
||||
Low level cleanup constructs (such as ``__free()``) can be used when building
|
||||
APIs and helpers, especially scoped iterators. However, direct use of
|
||||
``__free()`` within networking core and drivers is discouraged.
|
||||
Similar guidance applies to declaring variables mid-function.
|
||||
|
||||
Resending after review
|
||||
~~~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
|
@ -145,32 +145,32 @@ This is how a well-documented Rust function may look like:
|
||||
This example showcases a few ``rustdoc`` features and some conventions followed
|
||||
in the kernel:
|
||||
|
||||
- The first paragraph must be a single sentence briefly describing what
|
||||
the documented item does. Further explanations must go in extra paragraphs.
|
||||
- The first paragraph must be a single sentence briefly describing what
|
||||
the documented item does. Further explanations must go in extra paragraphs.
|
||||
|
||||
- Unsafe functions must document their safety preconditions under
|
||||
a ``# Safety`` section.
|
||||
- Unsafe functions must document their safety preconditions under
|
||||
a ``# Safety`` section.
|
||||
|
||||
- While not shown here, if a function may panic, the conditions under which
|
||||
that happens must be described under a ``# Panics`` section.
|
||||
- While not shown here, if a function may panic, the conditions under which
|
||||
that happens must be described under a ``# Panics`` section.
|
||||
|
||||
Please note that panicking should be very rare and used only with a good
|
||||
reason. In almost all cases, a fallible approach should be used, typically
|
||||
returning a ``Result``.
|
||||
Please note that panicking should be very rare and used only with a good
|
||||
reason. In almost all cases, a fallible approach should be used, typically
|
||||
returning a ``Result``.
|
||||
|
||||
- If providing examples of usage would help readers, they must be written in
|
||||
a section called ``# Examples``.
|
||||
- If providing examples of usage would help readers, they must be written in
|
||||
a section called ``# Examples``.
|
||||
|
||||
- Rust items (functions, types, constants...) must be linked appropriately
|
||||
(``rustdoc`` will create a link automatically).
|
||||
- Rust items (functions, types, constants...) must be linked appropriately
|
||||
(``rustdoc`` will create a link automatically).
|
||||
|
||||
- Any ``unsafe`` block must be preceded by a ``// SAFETY:`` comment
|
||||
describing why the code inside is sound.
|
||||
- Any ``unsafe`` block must be preceded by a ``// SAFETY:`` comment
|
||||
describing why the code inside is sound.
|
||||
|
||||
While sometimes the reason might look trivial and therefore unneeded,
|
||||
writing these comments is not just a good way of documenting what has been
|
||||
taken into account, but most importantly, it provides a way to know that
|
||||
there are no *extra* implicit constraints.
|
||||
While sometimes the reason might look trivial and therefore unneeded,
|
||||
writing these comments is not just a good way of documenting what has been
|
||||
taken into account, but most importantly, it provides a way to know that
|
||||
there are no *extra* implicit constraints.
|
||||
|
||||
To learn more about how to write documentation for Rust and extra features,
|
||||
please take a look at the ``rustdoc`` book at:
|
||||
|
@ -305,7 +305,7 @@ If GDB/Binutils is used and Rust symbols are not getting demangled, the reason
|
||||
is the toolchain does not support Rust's new v0 mangling scheme yet.
|
||||
There are a few ways out:
|
||||
|
||||
- Install a newer release (GDB >= 10.2, Binutils >= 2.36).
|
||||
- Install a newer release (GDB >= 10.2, Binutils >= 2.36).
|
||||
|
||||
- Some versions of GDB (e.g. vanilla GDB 10.1) are able to use
|
||||
the pre-demangled names embedded in the debug info (``CONFIG_DEBUG_INFO``).
|
||||
- Some versions of GDB (e.g. vanilla GDB 10.1) are able to use
|
||||
the pre-demangled names embedded in the debug info (``CONFIG_DEBUG_INFO``).
|
||||
|
46
MAINTAINERS
46
MAINTAINERS
@ -1888,6 +1888,10 @@ F: Documentation/devicetree/bindings/iommu/arm,smmu*
|
||||
F: drivers/iommu/arm/
|
||||
F: drivers/iommu/io-pgtable-arm*
|
||||
|
||||
ARM SMMU SVA SUPPORT
|
||||
R: Jean-Philippe Brucker <jean-philippe@linaro.org>
|
||||
F: drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
|
||||
|
||||
ARM SUB-ARCHITECTURES
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
@ -2543,8 +2547,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Supported
|
||||
W: http://www.linux4sam.org
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git
|
||||
F: arch/arm/boot/dts/microchip/at91*
|
||||
F: arch/arm/boot/dts/microchip/sama*
|
||||
F: arch/arm/boot/dts/microchip/
|
||||
F: arch/arm/include/debug/at91.S
|
||||
F: arch/arm/mach-at91/
|
||||
F: drivers/memory/atmel*
|
||||
@ -2753,7 +2756,7 @@ F: include/linux/soc/qcom/
|
||||
|
||||
ARM/QUALCOMM SUPPORT
|
||||
M: Bjorn Andersson <andersson@kernel.org>
|
||||
M: Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
M: Konrad Dybcio <konradybcio@kernel.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git
|
||||
@ -3873,7 +3876,7 @@ F: kernel/trace/blktrace.c
|
||||
F: lib/sbitmap.c
|
||||
|
||||
BLOCK LAYER DEVICE DRIVER API [RUST]
|
||||
M: Andreas Hindborg <a.hindborg@samsung.com>
|
||||
M: Andreas Hindborg <a.hindborg@kernel.org>
|
||||
R: Boqun Feng <boqun.feng@gmail.com>
|
||||
L: linux-block@vger.kernel.org
|
||||
L: rust-for-linux@vger.kernel.org
|
||||
@ -5961,6 +5964,7 @@ F: Documentation/process/cve.rst
|
||||
CW1200 WLAN driver
|
||||
S: Orphan
|
||||
F: drivers/net/wireless/st/cw1200/
|
||||
F: include/linux/platform_data/net-cw1200.h
|
||||
|
||||
CX18 VIDEO4LINUX DRIVER
|
||||
M: Andy Walls <awalls@md.metrocast.net>
|
||||
@ -7117,7 +7121,7 @@ F: drivers/gpu/drm/tiny/panel-mipi-dbi.c
|
||||
DRM DRIVER for Qualcomm Adreno GPUs
|
||||
M: Rob Clark <robdclark@gmail.com>
|
||||
R: Sean Paul <sean@poorly.run>
|
||||
R: Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
R: Konrad Dybcio <konradybcio@kernel.org>
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
L: dri-devel@lists.freedesktop.org
|
||||
L: freedreno@lists.freedesktop.org
|
||||
@ -7463,8 +7467,8 @@ S: Maintained
|
||||
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
|
||||
F: Documentation/devicetree/bindings/display/bridge/
|
||||
F: drivers/gpu/drm/bridge/
|
||||
F: drivers/gpu/drm/display/drm_bridge_connector.c
|
||||
F: drivers/gpu/drm/drm_bridge.c
|
||||
F: drivers/gpu/drm/drm_bridge_connector.c
|
||||
F: include/drm/drm_bridge.h
|
||||
F: include/drm/drm_bridge_connector.h
|
||||
|
||||
@ -8869,6 +8873,7 @@ F: drivers/dma/fsldma.*
|
||||
FREESCALE DSPI DRIVER
|
||||
M: Vladimir Oltean <olteanv@gmail.com>
|
||||
L: linux-spi@vger.kernel.org
|
||||
L: imx@lists.linux.dev
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/spi/fsl,dspi*.yaml
|
||||
F: drivers/spi/spi-fsl-dspi.c
|
||||
@ -8953,6 +8958,14 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/i2c/i2c-imx-lpi2c.yaml
|
||||
F: drivers/i2c/busses/i2c-imx-lpi2c.c
|
||||
|
||||
FREESCALE IMX LPSPI DRIVER
|
||||
M: Frank Li <Frank.Li@nxp.com>
|
||||
L: linux-spi@vger.kernel.org
|
||||
L: imx@lists.linux.dev
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml
|
||||
F: drivers/spi/spi-fsl-lpspi.c
|
||||
|
||||
FREESCALE MPC I2C DRIVER
|
||||
M: Chris Packham <chris.packham@alliedtelesis.co.nz>
|
||||
L: linux-i2c@vger.kernel.org
|
||||
@ -8989,6 +9002,7 @@ F: include/linux/fsl/ptp_qoriq.h
|
||||
FREESCALE QUAD SPI DRIVER
|
||||
M: Han Xu <han.xu@nxp.com>
|
||||
L: linux-spi@vger.kernel.org
|
||||
L: imx@lists.linux.dev
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/spi/fsl,spi-fsl-qspi.yaml
|
||||
F: drivers/spi/spi-fsl-qspi.c
|
||||
@ -12176,7 +12190,7 @@ KERNEL NFSD, SUNRPC, AND LOCKD SERVERS
|
||||
M: Chuck Lever <chuck.lever@oracle.com>
|
||||
M: Jeff Layton <jlayton@kernel.org>
|
||||
R: Neil Brown <neilb@suse.de>
|
||||
R: Olga Kornievskaia <kolga@netapp.com>
|
||||
R: Olga Kornievskaia <okorniev@redhat.com>
|
||||
R: Dai Ngo <Dai.Ngo@oracle.com>
|
||||
R: Tom Talpey <tom@talpey.com>
|
||||
L: linux-nfs@vger.kernel.org
|
||||
@ -15901,6 +15915,8 @@ F: include/uapi/linux/ethtool_netlink.h
|
||||
F: include/uapi/linux/if_*
|
||||
F: include/uapi/linux/netdev*
|
||||
F: tools/testing/selftests/drivers/net/
|
||||
X: Documentation/devicetree/bindings/net/bluetooth/
|
||||
X: Documentation/devicetree/bindings/net/wireless/
|
||||
X: drivers/net/wireless/
|
||||
|
||||
NETWORKING DRIVERS (WIRELESS)
|
||||
@ -16414,6 +16430,7 @@ M: Han Xu <han.xu@nxp.com>
|
||||
M: Haibo Chen <haibo.chen@nxp.com>
|
||||
R: Yogesh Gaur <yogeshgaur.83@gmail.com>
|
||||
L: linux-spi@vger.kernel.org
|
||||
L: imx@lists.linux.dev
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/spi/spi-nxp-fspi.yaml
|
||||
F: drivers/spi/spi-nxp-fspi.c
|
||||
@ -17125,7 +17142,7 @@ F: include/dt-bindings/
|
||||
|
||||
OPENCOMPUTE PTP CLOCK DRIVER
|
||||
M: Jonathan Lemon <jonathan.lemon@gmail.com>
|
||||
M: Vadim Fedorenko <vadfed@linux.dev>
|
||||
M: Vadim Fedorenko <vadim.fedorenko@linux.dev>
|
||||
L: netdev@vger.kernel.org
|
||||
S: Maintained
|
||||
F: drivers/ptp/ptp_ocp.c
|
||||
@ -17444,6 +17461,7 @@ M: Roy Zang <roy.zang@nxp.com>
|
||||
L: linuxppc-dev@lists.ozlabs.org
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: imx@lists.linux.dev
|
||||
S: Maintained
|
||||
F: drivers/pci/controller/dwc/*layerscape*
|
||||
|
||||
@ -17470,6 +17488,7 @@ M: Richard Zhu <hongxing.zhu@nxp.com>
|
||||
M: Lucas Stach <l.stach@pengutronix.de>
|
||||
L: linux-pci@vger.kernel.org
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: imx@lists.linux.dev
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
|
||||
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
|
||||
@ -17648,6 +17667,7 @@ F: drivers/pci/controller/pci-xgene-msi.c
|
||||
PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS
|
||||
M: Lorenzo Pieralisi <lpieralisi@kernel.org>
|
||||
M: Krzysztof Wilczyński <kw@linux.com>
|
||||
R: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
|
||||
R: Rob Herring <robh@kernel.org>
|
||||
L: linux-pci@vger.kernel.org
|
||||
S: Supported
|
||||
@ -18554,7 +18574,6 @@ F: drivers/crypto/intel/qat/
|
||||
|
||||
QCOM AUDIO (ASoC) DRIVERS
|
||||
M: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
|
||||
M: Banajit Goswami <bgoswami@quicinc.com>
|
||||
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Supported
|
||||
@ -18802,7 +18821,7 @@ F: include/uapi/drm/qaic_accel.h
|
||||
|
||||
QUALCOMM CORE POWER REDUCTION (CPR) AVS DRIVER
|
||||
M: Bjorn Andersson <andersson@kernel.org>
|
||||
M: Konrad Dybcio <konrad.dybcio@linaro.org>
|
||||
M: Konrad Dybcio <konradybcio@kernel.org>
|
||||
L: linux-pm@vger.kernel.org
|
||||
L: linux-arm-msm@vger.kernel.org
|
||||
S: Maintained
|
||||
@ -19935,12 +19954,11 @@ F: tools/verification/
|
||||
RUST
|
||||
M: Miguel Ojeda <ojeda@kernel.org>
|
||||
M: Alex Gaynor <alex.gaynor@gmail.com>
|
||||
M: Wedson Almeida Filho <wedsonaf@gmail.com>
|
||||
R: Boqun Feng <boqun.feng@gmail.com>
|
||||
R: Gary Guo <gary@garyguo.net>
|
||||
R: Björn Roy Baron <bjorn3_gh@protonmail.com>
|
||||
R: Benno Lossin <benno.lossin@proton.me>
|
||||
R: Andreas Hindborg <a.hindborg@samsung.com>
|
||||
R: Andreas Hindborg <a.hindborg@kernel.org>
|
||||
R: Alice Ryhl <aliceryhl@google.com>
|
||||
L: rust-for-linux@vger.kernel.org
|
||||
S: Supported
|
||||
@ -23851,10 +23869,8 @@ F: drivers/media/usb/uvc/
|
||||
F: include/uapi/linux/uvcvideo.h
|
||||
|
||||
USB WEBCAM GADGET
|
||||
M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
|
||||
M: Daniel Scally <dan.scally@ideasonboard.com>
|
||||
L: linux-usb@vger.kernel.org
|
||||
S: Maintained
|
||||
S: Orphan
|
||||
F: drivers/usb/gadget/function/*uvc*
|
||||
F: drivers/usb/gadget/legacy/webcam.c
|
||||
F: include/uapi/linux/usb/g_uvc.h
|
||||
|
3
Makefile
3
Makefile
@ -2,7 +2,7 @@
|
||||
VERSION = 6
|
||||
PATCHLEVEL = 11
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc5
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = Baby Opossum Posse
|
||||
|
||||
# *DOCUMENTATION*
|
||||
@ -445,6 +445,7 @@ KBUILD_USERLDFLAGS := $(USERLDFLAGS)
|
||||
# host programs.
|
||||
export rust_common_flags := --edition=2021 \
|
||||
-Zbinary_dep_depinfo=y \
|
||||
-Astable_features \
|
||||
-Dunsafe_op_in_unsafe_fn \
|
||||
-Dnon_ascii_idents \
|
||||
-Wrust_2018_idioms \
|
||||
|
@ -117,7 +117,7 @@ config ARM
|
||||
select HAVE_KERNEL_XZ
|
||||
select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
|
||||
select HAVE_KRETPROBES if HAVE_KPROBES
|
||||
select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
|
||||
select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD)
|
||||
select HAVE_MOD_ARCH_SPECIFIC
|
||||
select HAVE_NMI
|
||||
select HAVE_OPTPROBES if !THUMB2_KERNEL
|
||||
|
@ -274,24 +274,24 @@
|
||||
|
||||
led@0 {
|
||||
chan-name = "R";
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
led-cur = /bits/ 8 <0x6e>;
|
||||
max-cur = /bits/ 8 <0xc8>;
|
||||
reg = <0>;
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
};
|
||||
|
||||
led@1 {
|
||||
chan-name = "G";
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
led-cur = /bits/ 8 <0xbe>;
|
||||
max-cur = /bits/ 8 <0xc8>;
|
||||
reg = <1>;
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
};
|
||||
|
||||
led@2 {
|
||||
chan-name = "B";
|
||||
led-cur = /bits/ 8 <0x20>;
|
||||
max-cur = /bits/ 8 <0x60>;
|
||||
led-cur = /bits/ 8 <0xbe>;
|
||||
max-cur = /bits/ 8 <0xc8>;
|
||||
reg = <2>;
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
};
|
||||
|
@ -781,7 +781,7 @@
|
||||
|
||||
mount-matrix = "-1", "0", "0",
|
||||
"0", "1", "0",
|
||||
"0", "0", "1";
|
||||
"0", "0", "-1";
|
||||
};
|
||||
|
||||
cam1: camera@3e {
|
||||
|
@ -29,6 +29,12 @@
|
||||
#include "entry-header.S"
|
||||
#include <asm/probes.h>
|
||||
|
||||
#ifdef CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION
|
||||
#define RELOC_TEXT_NONE .reloc .text, R_ARM_NONE, .
|
||||
#else
|
||||
#define RELOC_TEXT_NONE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Interrupt handling.
|
||||
*/
|
||||
@ -1065,7 +1071,7 @@ vector_addrexcptn:
|
||||
.globl vector_fiq
|
||||
|
||||
.section .vectors, "ax", %progbits
|
||||
.reloc .text, R_ARM_NONE, .
|
||||
RELOC_TEXT_NONE
|
||||
W(b) vector_rst
|
||||
W(b) vector_und
|
||||
ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_swi )
|
||||
@ -1079,7 +1085,7 @@ THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_swi )
|
||||
|
||||
#ifdef CONFIG_HARDEN_BRANCH_HISTORY
|
||||
.section .vectors.bhb.loop8, "ax", %progbits
|
||||
.reloc .text, R_ARM_NONE, .
|
||||
RELOC_TEXT_NONE
|
||||
W(b) vector_rst
|
||||
W(b) vector_bhb_loop8_und
|
||||
ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_loop8_swi )
|
||||
@ -1092,7 +1098,7 @@ THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_loop8_swi )
|
||||
W(b) vector_bhb_loop8_fiq
|
||||
|
||||
.section .vectors.bhb.bpiall, "ax", %progbits
|
||||
.reloc .text, R_ARM_NONE, .
|
||||
RELOC_TEXT_NONE
|
||||
W(b) vector_rst
|
||||
W(b) vector_bhb_bpiall_und
|
||||
ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_bpiall_swi )
|
||||
|
@ -175,7 +175,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
core-cluster-thermal {
|
||||
cluster-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 1>;
|
||||
|
@ -214,7 +214,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
core-cluster-thermal {
|
||||
cluster-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 3>;
|
||||
|
@ -182,7 +182,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
core-cluster-thermal {
|
||||
cluster-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 3>;
|
||||
|
@ -131,7 +131,7 @@
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
core-cluster-thermal {
|
||||
cluster-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 0>;
|
||||
|
@ -122,7 +122,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
core-cluster1-thermal {
|
||||
cluster1-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 4>;
|
||||
@ -151,7 +151,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
core-cluster2-thermal {
|
||||
cluster2-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 5>;
|
||||
@ -180,7 +180,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
core-cluster3-thermal {
|
||||
cluster3-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 6>;
|
||||
@ -209,7 +209,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
core-cluster4-thermal {
|
||||
cluster4-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 7>;
|
||||
|
@ -492,7 +492,7 @@
|
||||
};
|
||||
};
|
||||
|
||||
ddr-cluster5-thermal {
|
||||
ddr-ctrl5-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <5000>;
|
||||
thermal-sensors = <&tmu 1>;
|
||||
|
@ -21,7 +21,7 @@
|
||||
|
||||
&gpio3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrcl-0 = <&pinctrl_gpio3_hog>;
|
||||
pinctrl-0 = <&pinctrl_gpio3_hog>;
|
||||
|
||||
uart4_rs485_en {
|
||||
gpio-hog;
|
||||
|
@ -22,7 +22,7 @@
|
||||
|
||||
&gpio3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrcl-0 = <&pinctrl_gpio3_hog>;
|
||||
pinctrl-0 = <&pinctrl_gpio3_hog>;
|
||||
|
||||
uart4_rs485_en {
|
||||
gpio-hog;
|
||||
|
@ -211,13 +211,12 @@
|
||||
|
||||
simple-audio-card,cpu {
|
||||
sound-dai = <&sai3>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
|
||||
simple-audio-card,codec {
|
||||
sound-dai = <&wm8962>;
|
||||
clocks = <&clk IMX8MP_CLK_IPP_DO_CLKO1>;
|
||||
frame-master;
|
||||
bitclock-master;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -507,10 +506,9 @@
|
||||
&sai3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai3>;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_SAI3>,
|
||||
<&clk IMX8MP_AUDIO_PLL2> ;
|
||||
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
|
||||
assigned-clock-rates = <12288000>, <361267200>;
|
||||
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
|
||||
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
|
||||
assigned-clock-rates = <12288000>;
|
||||
fsl,sai-mclk-direction-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
@ -499,7 +499,7 @@
|
||||
pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
|
||||
pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>;
|
||||
cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>;
|
||||
cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <®_usdhc2_vmmc>;
|
||||
bus-width = <4>;
|
||||
no-sdio;
|
||||
|
@ -19,7 +19,7 @@
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
alloc-ranges = <0 0x60000000 0 0x40000000>;
|
||||
alloc-ranges = <0 0x80000000 0 0x40000000>;
|
||||
size = <0 0x10000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
@ -156,6 +156,7 @@
|
||||
&wdog3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,ext-reset-output;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -1105,7 +1105,7 @@
|
||||
<&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
|
||||
assigned-clock-rates = <100000000>, <250000000>;
|
||||
intf_mode = <&wakeupmix_gpr 0x28>;
|
||||
snps,clk-csr = <0>;
|
||||
snps,clk-csr = <6>;
|
||||
nvmem-cells = <ð_mac2>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
status = "disabled";
|
||||
|
@ -27,7 +27,7 @@
|
||||
reg = <0x0>;
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
power-domains = <&scmi_devpd IMX95_PERF_A55>;
|
||||
power-domains = <&scmi_perf IMX95_PERF_A55>;
|
||||
power-domain-names = "perf";
|
||||
i-cache-size = <32768>;
|
||||
i-cache-line-size = <64>;
|
||||
@ -44,7 +44,7 @@
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
power-domains = <&scmi_devpd IMX95_PERF_A55>;
|
||||
power-domains = <&scmi_perf IMX95_PERF_A55>;
|
||||
power-domain-names = "perf";
|
||||
i-cache-size = <32768>;
|
||||
i-cache-line-size = <64>;
|
||||
@ -61,7 +61,7 @@
|
||||
reg = <0x200>;
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
power-domains = <&scmi_devpd IMX95_PERF_A55>;
|
||||
power-domains = <&scmi_perf IMX95_PERF_A55>;
|
||||
power-domain-names = "perf";
|
||||
i-cache-size = <32768>;
|
||||
i-cache-line-size = <64>;
|
||||
@ -78,7 +78,7 @@
|
||||
reg = <0x300>;
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
power-domains = <&scmi_devpd IMX95_PERF_A55>;
|
||||
power-domains = <&scmi_perf IMX95_PERF_A55>;
|
||||
power-domain-names = "perf";
|
||||
i-cache-size = <32768>;
|
||||
i-cache-line-size = <64>;
|
||||
@ -93,7 +93,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x400>;
|
||||
power-domains = <&scmi_devpd IMX95_PERF_A55>;
|
||||
power-domains = <&scmi_perf IMX95_PERF_A55>;
|
||||
power-domain-names = "perf";
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
@ -110,7 +110,7 @@
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a55";
|
||||
reg = <0x500>;
|
||||
power-domains = <&scmi_devpd IMX95_PERF_A55>;
|
||||
power-domains = <&scmi_perf IMX95_PERF_A55>;
|
||||
power-domain-names = "perf";
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
@ -187,7 +187,7 @@
|
||||
compatible = "cache";
|
||||
cache-size = <524288>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
cache-sets = <512>;
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
|
@ -320,8 +320,8 @@
|
||||
reg = <0x08af8800 0x400>;
|
||||
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_EDGE_BOTH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_EDGE_BOTH>;
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "pwr_event",
|
||||
"dp_hs_phy_irq",
|
||||
"dm_hs_phy_irq";
|
||||
|
@ -278,6 +278,13 @@
|
||||
vdd-l3-supply = <&vreg_s1f_0p7>;
|
||||
vdd-s1-supply = <&vph_pwr>;
|
||||
vdd-s2-supply = <&vph_pwr>;
|
||||
|
||||
vreg_l3i_0p8: ldo3 {
|
||||
regulator-name = "vreg_l3i_0p8";
|
||||
regulator-min-microvolt = <880000>;
|
||||
regulator-max-microvolt = <920000>;
|
||||
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators-7 {
|
||||
@ -423,11 +430,17 @@
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
@ -517,7 +530,30 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie2a-default-state {
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
@ -529,7 +565,7 @@
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
|
@ -268,7 +268,6 @@
|
||||
pinctrl-0 = <&edp_reg_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
@ -637,6 +636,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
|
||||
zap-shader {
|
||||
firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
clock-frequency = <400000>;
|
||||
|
||||
@ -724,9 +731,13 @@
|
||||
|
||||
aux-bus {
|
||||
panel {
|
||||
compatible = "edp-panel";
|
||||
compatible = "samsung,atna45af01", "samsung,atna33xc20";
|
||||
enable-gpios = <&pmc8380_3_gpios 4 GPIO_ACTIVE_HIGH>;
|
||||
power-supply = <&vreg_edp_3p3>;
|
||||
|
||||
pinctrl-0 = <&edp_bl_en>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
port {
|
||||
edp_panel_in: endpoint {
|
||||
remote-endpoint = <&mdss_dp3_out>;
|
||||
@ -756,11 +767,17 @@
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
@ -785,6 +802,16 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pmc8380_3_gpios {
|
||||
edp_bl_en: edp-bl-en-state {
|
||||
pins = "gpio4";
|
||||
function = "normal";
|
||||
power-source = <1>; /* 1.8V */
|
||||
input-disable;
|
||||
output-enable;
|
||||
};
|
||||
};
|
||||
|
||||
&qupv3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
@ -931,7 +958,30 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie2a-default-state {
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
@ -943,15 +993,15 @@
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
tpad_default: tpad-default-state {
|
||||
|
@ -625,16 +625,31 @@
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_port0 {
|
||||
wifi@0 {
|
||||
compatible = "pci17cb,1107";
|
||||
reg = <0x10000 0x0 0x0 0x0 0x0>;
|
||||
|
||||
qcom,ath12k-calibration-variant = "LES790";
|
||||
};
|
||||
};
|
||||
|
||||
&pcie6a {
|
||||
perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>;
|
||||
@ -782,7 +797,30 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie2a-default-state {
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
@ -794,15 +832,15 @@
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
tpad_default: tpad-default-state {
|
||||
|
@ -606,6 +606,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
|
||||
zap-shader {
|
||||
firmware-name = "qcom/x1e80100/gen70500_zap.mbn";
|
||||
};
|
||||
};
|
||||
|
||||
&lpass_tlmm {
|
||||
spkr_01_sd_n_active: spkr-01-sd-n-active-state {
|
||||
pins = "gpio12";
|
||||
@ -660,11 +668,17 @@
|
||||
};
|
||||
|
||||
&pcie4 {
|
||||
perst-gpios = <&tlmm 146 GPIO_ACTIVE_LOW>;
|
||||
wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pinctrl-0 = <&pcie4_default>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie4_phy {
|
||||
vdda-phy-supply = <&vreg_l3j_0p8>;
|
||||
vdda-phy-supply = <&vreg_l3i_0p8>;
|
||||
vdda-pll-supply = <&vreg_l3e_1p2>;
|
||||
|
||||
status = "okay";
|
||||
@ -804,7 +818,30 @@
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pcie6a_default: pcie2a-default-state {
|
||||
pcie4_default: pcie4-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio147";
|
||||
function = "pcie4_clk";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
perst-n-pins {
|
||||
pins = "gpio146";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio148";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pcie6a_default: pcie6a-default-state {
|
||||
clkreq-n-pins {
|
||||
pins = "gpio153";
|
||||
function = "pcie6a_clk";
|
||||
@ -816,15 +853,15 @@
|
||||
pins = "gpio152";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
wake-n-pins {
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
pins = "gpio154";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
wcd_default: wcd-reset-n-active-state {
|
||||
|
@ -2901,7 +2901,7 @@
|
||||
|
||||
dma-coherent;
|
||||
|
||||
linux,pci-domain = <7>;
|
||||
linux,pci-domain = <6>;
|
||||
num-lanes = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@ -2959,6 +2959,7 @@
|
||||
"link_down";
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_6A_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie6a_phy>;
|
||||
phy-names = "pciephy";
|
||||
@ -3022,7 +3023,7 @@
|
||||
|
||||
dma-coherent;
|
||||
|
||||
linux,pci-domain = <5>;
|
||||
linux,pci-domain = <4>;
|
||||
num-lanes = <2>;
|
||||
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
|
||||
@ -3080,11 +3081,22 @@
|
||||
"link_down";
|
||||
|
||||
power-domains = <&gcc GCC_PCIE_4_GDSC>;
|
||||
required-opps = <&rpmhpd_opp_nom>;
|
||||
|
||||
phys = <&pcie4_phy>;
|
||||
phy-names = "pciephy";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
pcie4_port0: pcie@0 {
|
||||
device_type = "pci";
|
||||
reg = <0x0 0x0 0x0 0x0 0x0>;
|
||||
bus-range = <0x01 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
pcie4_phy: phy@1c0e000 {
|
||||
@ -3155,9 +3167,10 @@
|
||||
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
|
||||
interconnect-names = "gfx-mem";
|
||||
|
||||
status = "disabled";
|
||||
|
||||
zap-shader {
|
||||
memory-region = <&gpu_microcode_mem>;
|
||||
firmware-name = "qcom/gen70500_zap.mbn";
|
||||
};
|
||||
|
||||
gpu_opp_table: opp-table {
|
||||
@ -3288,7 +3301,7 @@
|
||||
reg = <0x0 0x03da0000 0x0 0x40000>;
|
||||
#iommu-cells = <2>;
|
||||
#global-interrupts = <1>;
|
||||
interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
|
||||
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
|
||||
|
@ -887,6 +887,7 @@ CONFIG_DRM_PANEL_KHADAS_TS050=m
|
||||
CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
|
||||
CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
|
||||
CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
|
||||
CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
|
||||
CONFIG_DRM_PANEL_SITRONIX_ST7703=m
|
||||
CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
|
||||
CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
|
||||
|
@ -25,6 +25,7 @@
|
||||
*
|
||||
* @common: Common unwind state.
|
||||
* @task: The task being unwound.
|
||||
* @graph_idx: Used by ftrace_graph_ret_addr() for optimized stack unwinding.
|
||||
* @kr_cur: When KRETPROBES is selected, holds the kretprobe instance
|
||||
* associated with the most recently encountered replacement lr
|
||||
* value.
|
||||
@ -32,6 +33,7 @@
|
||||
struct kunwind_state {
|
||||
struct unwind_state common;
|
||||
struct task_struct *task;
|
||||
int graph_idx;
|
||||
#ifdef CONFIG_KRETPROBES
|
||||
struct llist_node *kr_cur;
|
||||
#endif
|
||||
@ -106,7 +108,7 @@ kunwind_recover_return_address(struct kunwind_state *state)
|
||||
if (state->task->ret_stack &&
|
||||
(state->common.pc == (unsigned long)return_to_handler)) {
|
||||
unsigned long orig_pc;
|
||||
orig_pc = ftrace_graph_ret_addr(state->task, NULL,
|
||||
orig_pc = ftrace_graph_ret_addr(state->task, &state->graph_idx,
|
||||
state->common.pc,
|
||||
(void *)state->common.fp);
|
||||
if (WARN_ON_ONCE(state->common.pc == orig_pc))
|
||||
|
@ -1,11 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
|
||||
*/
|
||||
#ifndef _LOONGARCH_DMA_DIRECT_H
|
||||
#define _LOONGARCH_DMA_DIRECT_H
|
||||
|
||||
dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr);
|
||||
phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr);
|
||||
|
||||
#endif /* _LOONGARCH_DMA_DIRECT_H */
|
@ -9,6 +9,8 @@
|
||||
|
||||
extern atomic_t irq_err_count;
|
||||
|
||||
#define ARCH_IRQ_INIT_FLAGS IRQ_NOPROBE
|
||||
|
||||
/*
|
||||
* interrupt-retrigger: NOP for now. This may not be appropriate for all
|
||||
* machines, we'll see ...
|
||||
|
@ -76,7 +76,6 @@ static inline void kvm_restore_lasx(struct loongarch_fpu *fpu) { }
|
||||
#endif
|
||||
|
||||
void kvm_init_timer(struct kvm_vcpu *vcpu, unsigned long hz);
|
||||
void kvm_reset_timer(struct kvm_vcpu *vcpu);
|
||||
void kvm_save_timer(struct kvm_vcpu *vcpu);
|
||||
void kvm_restore_timer(struct kvm_vcpu *vcpu);
|
||||
|
||||
|
@ -530,6 +530,10 @@ SYM_FUNC_END(_restore_lasx_context)
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_LBT
|
||||
STACK_FRAME_NON_STANDARD _restore_fp
|
||||
#ifdef CONFIG_CPU_HAS_LSX
|
||||
STACK_FRAME_NON_STANDARD _restore_lsx
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_HAS_LASX
|
||||
STACK_FRAME_NON_STANDARD _restore_lasx
|
||||
#endif
|
||||
#endif
|
||||
|
@ -102,9 +102,6 @@ void __init init_IRQ(void)
|
||||
mp_ops.init_ipi();
|
||||
#endif
|
||||
|
||||
for (i = 0; i < NR_IRQS; i++)
|
||||
irq_set_noprobe(i);
|
||||
|
||||
for_each_possible_cpu(i) {
|
||||
page = alloc_pages_node(cpu_to_node(i), GFP_KERNEL, order);
|
||||
|
||||
|
@ -277,6 +277,10 @@ SYM_DATA(kvm_enter_guest_size, .quad kvm_enter_guest_end - kvm_enter_guest)
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_LBT
|
||||
STACK_FRAME_NON_STANDARD kvm_restore_fpu
|
||||
#ifdef CONFIG_CPU_HAS_LSX
|
||||
STACK_FRAME_NON_STANDARD kvm_restore_lsx
|
||||
#endif
|
||||
#ifdef CONFIG_CPU_HAS_LASX
|
||||
STACK_FRAME_NON_STANDARD kvm_restore_lasx
|
||||
#endif
|
||||
#endif
|
||||
|
@ -188,10 +188,3 @@ void kvm_save_timer(struct kvm_vcpu *vcpu)
|
||||
kvm_save_hw_gcsr(csr, LOONGARCH_CSR_ESTAT);
|
||||
preempt_enable();
|
||||
}
|
||||
|
||||
void kvm_reset_timer(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
write_gcsr_timercfg(0);
|
||||
kvm_write_sw_gcsr(vcpu->arch.csr, LOONGARCH_CSR_TCFG, 0);
|
||||
hrtimer_cancel(&vcpu->arch.swtimer);
|
||||
}
|
||||
|
@ -647,7 +647,7 @@ static int kvm_set_one_reg(struct kvm_vcpu *vcpu,
|
||||
vcpu->kvm->arch.time_offset = (signed long)(v - drdtime());
|
||||
break;
|
||||
case KVM_REG_LOONGARCH_VCPU_RESET:
|
||||
kvm_reset_timer(vcpu);
|
||||
vcpu->arch.st.guest_addr = 0;
|
||||
memset(&vcpu->arch.irq_pending, 0, sizeof(vcpu->arch.irq_pending));
|
||||
memset(&vcpu->arch.irq_clear, 0, sizeof(vcpu->arch.irq_clear));
|
||||
break;
|
||||
|
@ -193,11 +193,6 @@ asmlinkage void __init mmu_init(void)
|
||||
{
|
||||
unsigned int kstart, ksize;
|
||||
|
||||
if (!memblock.reserved.cnt) {
|
||||
pr_emerg("Error memory count\n");
|
||||
machine_restart(NULL);
|
||||
}
|
||||
|
||||
if ((u32) memblock.memory.regions[0].size < 0x400000) {
|
||||
pr_emerg("Memory must be greater than 4MB\n");
|
||||
machine_restart(NULL);
|
||||
|
@ -21,9 +21,7 @@ static struct clocksource clocksource_mips = {
|
||||
.name = "MIPS",
|
||||
.read = c0_hpt_read,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS |
|
||||
CLOCK_SOURCE_MUST_VERIFY |
|
||||
CLOCK_SOURCE_VERIFY_PERCPU,
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static u64 __maybe_unused notrace r4k_read_sched_clock(void)
|
||||
|
@ -459,7 +459,6 @@ void free_initmem(void)
|
||||
unsigned long kernel_end = (unsigned long)&_end;
|
||||
|
||||
/* Remap kernel text and data, but do not touch init section yet. */
|
||||
kernel_set_to_readonly = true;
|
||||
map_pages(init_end, __pa(init_end), kernel_end - init_end,
|
||||
PAGE_KERNEL, 0);
|
||||
|
||||
@ -493,11 +492,18 @@ void free_initmem(void)
|
||||
#ifdef CONFIG_STRICT_KERNEL_RWX
|
||||
void mark_rodata_ro(void)
|
||||
{
|
||||
/* rodata memory was already mapped with KERNEL_RO access rights by
|
||||
pagetable_init() and map_pages(). No need to do additional stuff here */
|
||||
unsigned long roai_size = __end_ro_after_init - __start_ro_after_init;
|
||||
unsigned long start = (unsigned long) &__start_rodata;
|
||||
unsigned long end = (unsigned long) &__end_rodata;
|
||||
|
||||
pr_info("Write protected read-only-after-init data: %luk\n", roai_size >> 10);
|
||||
pr_info("Write protecting the kernel read-only data: %luk\n",
|
||||
(end - start) >> 10);
|
||||
|
||||
kernel_set_to_readonly = true;
|
||||
map_pages(start, __pa(start), end - start, PAGE_KERNEL, 0);
|
||||
|
||||
/* force the kernel to see the new page table entries */
|
||||
flush_cache_all();
|
||||
flush_tlb_all();
|
||||
}
|
||||
#endif
|
||||
|
||||
|
@ -52,7 +52,7 @@
|
||||
#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
|
||||
|
||||
#define pgd_ERROR(e) \
|
||||
pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
|
||||
pr_err("%s:%d: bad pgd %08llx.\n", __FILE__, __LINE__, (unsigned long long)pgd_val(e))
|
||||
|
||||
/*
|
||||
* This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
|
||||
@ -170,7 +170,7 @@ static inline void pmd_clear(pmd_t *pmdp)
|
||||
#define pmd_pfn(pmd) (pmd_val(pmd) >> PAGE_SHIFT)
|
||||
#else
|
||||
#define pmd_page_vaddr(pmd) \
|
||||
((const void *)(pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1)))
|
||||
((const void *)((unsigned long)pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1)))
|
||||
#define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT)
|
||||
#endif
|
||||
|
||||
|
@ -49,16 +49,22 @@ static inline unsigned long pud_val(pud_t x)
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
||||
/* PGD level */
|
||||
#if defined(CONFIG_PPC_E500) && defined(CONFIG_PTE_64BIT)
|
||||
#if defined(CONFIG_PPC_85xx) && defined(CONFIG_PTE_64BIT)
|
||||
typedef struct { unsigned long long pgd; } pgd_t;
|
||||
|
||||
static inline unsigned long long pgd_val(pgd_t x)
|
||||
{
|
||||
return x.pgd;
|
||||
}
|
||||
#else
|
||||
typedef struct { unsigned long pgd; } pgd_t;
|
||||
#endif
|
||||
#define __pgd(x) ((pgd_t) { (x) })
|
||||
|
||||
static inline unsigned long pgd_val(pgd_t x)
|
||||
{
|
||||
return x.pgd;
|
||||
}
|
||||
#endif
|
||||
#define __pgd(x) ((pgd_t) { (x) })
|
||||
|
||||
/* Page protection bits */
|
||||
typedef struct { unsigned long pgprot; } pgprot_t;
|
||||
|
@ -74,6 +74,8 @@ SECTIONS
|
||||
.got : { *(.got) } :text
|
||||
.plt : { *(.plt) }
|
||||
|
||||
.rela.dyn : { *(.rela .rela*) }
|
||||
|
||||
_end = .;
|
||||
__end = .;
|
||||
PROVIDE(end = .);
|
||||
@ -87,7 +89,7 @@ SECTIONS
|
||||
*(.branch_lt)
|
||||
*(.data .data.* .gnu.linkonce.d.* .sdata*)
|
||||
*(.bss .sbss .dynbss .dynsbss)
|
||||
*(.got1 .glink .iplt .rela*)
|
||||
*(.got1 .glink .iplt)
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -69,7 +69,7 @@ SECTIONS
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) } :text :eh_frame_hdr
|
||||
.eh_frame : { KEEP (*(.eh_frame)) } :text
|
||||
.gcc_except_table : { *(.gcc_except_table) }
|
||||
.rela.dyn ALIGN(8) : { *(.rela.dyn) }
|
||||
.rela.dyn ALIGN(8) : { *(.rela .rela*) }
|
||||
|
||||
.got ALIGN(8) : { *(.got .toc) }
|
||||
|
||||
@ -86,7 +86,7 @@ SECTIONS
|
||||
*(.data .data.* .gnu.linkonce.d.* .sdata*)
|
||||
*(.bss .sbss .dynbss .dynsbss)
|
||||
*(.opd)
|
||||
*(.glink .iplt .plt .rela*)
|
||||
*(.glink .iplt .plt)
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -697,7 +697,15 @@ again:
|
||||
}
|
||||
|
||||
release:
|
||||
qnodesp->count--; /* release the node */
|
||||
/*
|
||||
* Clear the lock before releasing the node, as another CPU might see stale
|
||||
* values if an interrupt occurs after we increment qnodesp->count
|
||||
* but before node->lock is initialized. The barrier ensures that
|
||||
* there are no further stores to the node after it has been released.
|
||||
*/
|
||||
node->lock = NULL;
|
||||
barrier();
|
||||
qnodesp->count--;
|
||||
}
|
||||
|
||||
void queued_spin_lock_slowpath(struct qspinlock *lock)
|
||||
|
@ -33,7 +33,7 @@
|
||||
* though this will probably be made common with other nohash
|
||||
* implementations at some point
|
||||
*/
|
||||
int mmu_pte_psize; /* Page size used for PTE pages */
|
||||
static int mmu_pte_psize; /* Page size used for PTE pages */
|
||||
int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
|
||||
int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
|
||||
unsigned long linear_map_top; /* Top of linear mapping */
|
||||
|
@ -552,8 +552,8 @@ config RISCV_ISA_SVPBMT
|
||||
config TOOLCHAIN_HAS_V
|
||||
bool
|
||||
default y
|
||||
depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64iv)
|
||||
depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32iv)
|
||||
depends on !64BIT || $(cc-option,-mabi=lp64 -march=rv64imv)
|
||||
depends on !32BIT || $(cc-option,-mabi=ilp32 -march=rv32imv)
|
||||
depends on LLD_VERSION >= 140000 || LD_VERSION >= 23800
|
||||
depends on AS_HAS_OPTION_ARCH
|
||||
|
||||
|
@ -14,36 +14,14 @@
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
/*
|
||||
* addr is a hint to the maximum userspace address that mmap should provide, so
|
||||
* this macro needs to return the largest address space available so that
|
||||
* mmap_end < addr, being mmap_end the top of that address space.
|
||||
* See Documentation/arch/riscv/vm-layout.rst for more details.
|
||||
*/
|
||||
#define arch_get_mmap_end(addr, len, flags) \
|
||||
({ \
|
||||
unsigned long mmap_end; \
|
||||
typeof(addr) _addr = (addr); \
|
||||
if ((_addr) == 0 || is_compat_task() || \
|
||||
((_addr + len) > BIT(VA_BITS - 1))) \
|
||||
mmap_end = STACK_TOP_MAX; \
|
||||
else \
|
||||
mmap_end = (_addr + len); \
|
||||
mmap_end; \
|
||||
STACK_TOP_MAX; \
|
||||
})
|
||||
|
||||
#define arch_get_mmap_base(addr, base) \
|
||||
({ \
|
||||
unsigned long mmap_base; \
|
||||
typeof(addr) _addr = (addr); \
|
||||
typeof(base) _base = (base); \
|
||||
unsigned long rnd_gap = DEFAULT_MAP_WINDOW - (_base); \
|
||||
if ((_addr) == 0 || is_compat_task() || \
|
||||
((_addr + len) > BIT(VA_BITS - 1))) \
|
||||
mmap_base = (_base); \
|
||||
else \
|
||||
mmap_base = (_addr + len) - rnd_gap; \
|
||||
mmap_base; \
|
||||
base; \
|
||||
})
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
|
@ -9,6 +9,7 @@
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/cpumask.h>
|
||||
#include <linux/jump_label.h>
|
||||
|
||||
#ifdef CONFIG_RISCV_SBI
|
||||
enum sbi_ext_id {
|
||||
@ -304,6 +305,7 @@ struct sbiret {
|
||||
};
|
||||
|
||||
void sbi_init(void);
|
||||
long __sbi_base_ecall(int fid);
|
||||
struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
|
||||
unsigned long arg2, unsigned long arg3,
|
||||
unsigned long arg4, unsigned long arg5,
|
||||
@ -373,7 +375,23 @@ static inline unsigned long sbi_mk_version(unsigned long major,
|
||||
| (minor & SBI_SPEC_VERSION_MINOR_MASK);
|
||||
}
|
||||
|
||||
int sbi_err_map_linux_errno(int err);
|
||||
static inline int sbi_err_map_linux_errno(int err)
|
||||
{
|
||||
switch (err) {
|
||||
case SBI_SUCCESS:
|
||||
return 0;
|
||||
case SBI_ERR_DENIED:
|
||||
return -EPERM;
|
||||
case SBI_ERR_INVALID_PARAM:
|
||||
return -EINVAL;
|
||||
case SBI_ERR_INVALID_ADDRESS:
|
||||
return -EFAULT;
|
||||
case SBI_ERR_NOT_SUPPORTED:
|
||||
case SBI_ERR_FAILURE:
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
};
|
||||
}
|
||||
|
||||
extern bool sbi_debug_console_available;
|
||||
int sbi_debug_console_write(const char *bytes, unsigned int num_bytes);
|
||||
|
@ -20,17 +20,21 @@ endif
|
||||
ifdef CONFIG_RISCV_ALTERNATIVE_EARLY
|
||||
CFLAGS_alternative.o := -mcmodel=medany
|
||||
CFLAGS_cpufeature.o := -mcmodel=medany
|
||||
CFLAGS_sbi_ecall.o := -mcmodel=medany
|
||||
ifdef CONFIG_FTRACE
|
||||
CFLAGS_REMOVE_alternative.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_cpufeature.o = $(CC_FLAGS_FTRACE)
|
||||
CFLAGS_REMOVE_sbi_ecall.o = $(CC_FLAGS_FTRACE)
|
||||
endif
|
||||
ifdef CONFIG_RELOCATABLE
|
||||
CFLAGS_alternative.o += -fno-pie
|
||||
CFLAGS_cpufeature.o += -fno-pie
|
||||
CFLAGS_sbi_ecall.o += -fno-pie
|
||||
endif
|
||||
ifdef CONFIG_KASAN
|
||||
KASAN_SANITIZE_alternative.o := n
|
||||
KASAN_SANITIZE_cpufeature.o := n
|
||||
KASAN_SANITIZE_sbi_ecall.o := n
|
||||
endif
|
||||
endif
|
||||
|
||||
@ -88,7 +92,7 @@ obj-$(CONFIG_DYNAMIC_FTRACE) += mcount-dyn.o
|
||||
|
||||
obj-$(CONFIG_PERF_EVENTS) += perf_callchain.o
|
||||
obj-$(CONFIG_HAVE_PERF_REGS) += perf_regs.o
|
||||
obj-$(CONFIG_RISCV_SBI) += sbi.o
|
||||
obj-$(CONFIG_RISCV_SBI) += sbi.o sbi_ecall.o
|
||||
ifeq ($(CONFIG_RISCV_SBI), y)
|
||||
obj-$(CONFIG_SMP) += sbi-ipi.o
|
||||
obj-$(CONFIG_SMP) += cpu_ops_sbi.o
|
||||
|
@ -14,9 +14,6 @@
|
||||
#include <asm/smp.h>
|
||||
#include <asm/tlbflush.h>
|
||||
|
||||
#define CREATE_TRACE_POINTS
|
||||
#include <asm/trace.h>
|
||||
|
||||
/* default SBI version is 0.1 */
|
||||
unsigned long sbi_spec_version __ro_after_init = SBI_SPEC_VERSION_DEFAULT;
|
||||
EXPORT_SYMBOL(sbi_spec_version);
|
||||
@ -27,55 +24,6 @@ static int (*__sbi_rfence)(int fid, const struct cpumask *cpu_mask,
|
||||
unsigned long start, unsigned long size,
|
||||
unsigned long arg4, unsigned long arg5) __ro_after_init;
|
||||
|
||||
struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
|
||||
unsigned long arg2, unsigned long arg3,
|
||||
unsigned long arg4, unsigned long arg5,
|
||||
int fid, int ext)
|
||||
{
|
||||
struct sbiret ret;
|
||||
|
||||
trace_sbi_call(ext, fid);
|
||||
|
||||
register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
|
||||
register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
|
||||
register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
|
||||
register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
|
||||
register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
|
||||
register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
|
||||
register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
|
||||
register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
|
||||
asm volatile ("ecall"
|
||||
: "+r" (a0), "+r" (a1)
|
||||
: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
|
||||
: "memory");
|
||||
ret.error = a0;
|
||||
ret.value = a1;
|
||||
|
||||
trace_sbi_return(ext, ret.error, ret.value);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(__sbi_ecall);
|
||||
|
||||
int sbi_err_map_linux_errno(int err)
|
||||
{
|
||||
switch (err) {
|
||||
case SBI_SUCCESS:
|
||||
return 0;
|
||||
case SBI_ERR_DENIED:
|
||||
return -EPERM;
|
||||
case SBI_ERR_INVALID_PARAM:
|
||||
return -EINVAL;
|
||||
case SBI_ERR_INVALID_ADDRESS:
|
||||
return -EFAULT;
|
||||
case SBI_ERR_NOT_SUPPORTED:
|
||||
case SBI_ERR_FAILURE:
|
||||
default:
|
||||
return -ENOTSUPP;
|
||||
};
|
||||
}
|
||||
EXPORT_SYMBOL(sbi_err_map_linux_errno);
|
||||
|
||||
#ifdef CONFIG_RISCV_SBI_V01
|
||||
static unsigned long __sbi_v01_cpumask_to_hartmask(const struct cpumask *cpu_mask)
|
||||
{
|
||||
@ -535,17 +483,6 @@ long sbi_probe_extension(int extid)
|
||||
}
|
||||
EXPORT_SYMBOL(sbi_probe_extension);
|
||||
|
||||
static long __sbi_base_ecall(int fid)
|
||||
{
|
||||
struct sbiret ret;
|
||||
|
||||
ret = sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0);
|
||||
if (!ret.error)
|
||||
return ret.value;
|
||||
else
|
||||
return sbi_err_map_linux_errno(ret.error);
|
||||
}
|
||||
|
||||
static inline long sbi_get_spec_version(void)
|
||||
{
|
||||
return __sbi_base_ecall(SBI_EXT_BASE_GET_SPEC_VERSION);
|
||||
|
48
arch/riscv/kernel/sbi_ecall.c
Normal file
48
arch/riscv/kernel/sbi_ecall.c
Normal file
@ -0,0 +1,48 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/* Copyright (c) 2024 Rivos Inc. */
|
||||
|
||||
#include <asm/sbi.h>
|
||||
#define CREATE_TRACE_POINTS
|
||||
#include <asm/trace.h>
|
||||
|
||||
long __sbi_base_ecall(int fid)
|
||||
{
|
||||
struct sbiret ret;
|
||||
|
||||
ret = sbi_ecall(SBI_EXT_BASE, fid, 0, 0, 0, 0, 0, 0);
|
||||
if (!ret.error)
|
||||
return ret.value;
|
||||
else
|
||||
return sbi_err_map_linux_errno(ret.error);
|
||||
}
|
||||
EXPORT_SYMBOL(__sbi_base_ecall);
|
||||
|
||||
struct sbiret __sbi_ecall(unsigned long arg0, unsigned long arg1,
|
||||
unsigned long arg2, unsigned long arg3,
|
||||
unsigned long arg4, unsigned long arg5,
|
||||
int fid, int ext)
|
||||
{
|
||||
struct sbiret ret;
|
||||
|
||||
trace_sbi_call(ext, fid);
|
||||
|
||||
register uintptr_t a0 asm ("a0") = (uintptr_t)(arg0);
|
||||
register uintptr_t a1 asm ("a1") = (uintptr_t)(arg1);
|
||||
register uintptr_t a2 asm ("a2") = (uintptr_t)(arg2);
|
||||
register uintptr_t a3 asm ("a3") = (uintptr_t)(arg3);
|
||||
register uintptr_t a4 asm ("a4") = (uintptr_t)(arg4);
|
||||
register uintptr_t a5 asm ("a5") = (uintptr_t)(arg5);
|
||||
register uintptr_t a6 asm ("a6") = (uintptr_t)(fid);
|
||||
register uintptr_t a7 asm ("a7") = (uintptr_t)(ext);
|
||||
asm volatile ("ecall"
|
||||
: "+r" (a0), "+r" (a1)
|
||||
: "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7)
|
||||
: "memory");
|
||||
ret.error = a0;
|
||||
ret.value = a1;
|
||||
|
||||
trace_sbi_return(ext, ret.error, ret.value);
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL(__sbi_ecall);
|
@ -417,7 +417,7 @@ int handle_misaligned_load(struct pt_regs *regs)
|
||||
|
||||
val.data_u64 = 0;
|
||||
if (user_mode(regs)) {
|
||||
if (raw_copy_from_user(&val, (u8 __user *)addr, len))
|
||||
if (copy_from_user(&val, (u8 __user *)addr, len))
|
||||
return -1;
|
||||
} else {
|
||||
memcpy(&val, (u8 *)addr, len);
|
||||
@ -515,7 +515,7 @@ int handle_misaligned_store(struct pt_regs *regs)
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (user_mode(regs)) {
|
||||
if (raw_copy_to_user((u8 __user *)addr, &val, len))
|
||||
if (copy_to_user((u8 __user *)addr, &val, len))
|
||||
return -1;
|
||||
} else {
|
||||
memcpy((u8 *)addr, &val, len);
|
||||
|
@ -252,7 +252,7 @@ static void __init setup_bootmem(void)
|
||||
* The size of the linear page mapping may restrict the amount of
|
||||
* usable RAM.
|
||||
*/
|
||||
if (IS_ENABLED(CONFIG_64BIT)) {
|
||||
if (IS_ENABLED(CONFIG_64BIT) && IS_ENABLED(CONFIG_MMU)) {
|
||||
max_mapped_addr = __pa(PAGE_OFFSET) + KERN_VIRT_SIZE;
|
||||
memblock_cap_memory_range(phys_ram_base,
|
||||
max_mapped_addr - phys_ram_base);
|
||||
|
@ -389,7 +389,6 @@ static bool mmio_read(int size, unsigned long addr, unsigned long *val)
|
||||
.r12 = size,
|
||||
.r13 = EPT_READ,
|
||||
.r14 = addr,
|
||||
.r15 = *val,
|
||||
};
|
||||
|
||||
if (__tdx_hypercall(&args))
|
||||
|
@ -4589,6 +4589,25 @@ static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void)
|
||||
return HYBRID_INTEL_CORE;
|
||||
}
|
||||
|
||||
static inline bool erratum_hsw11(struct perf_event *event)
|
||||
{
|
||||
return (event->hw.config & INTEL_ARCH_EVENT_MASK) ==
|
||||
X86_CONFIG(.event=0xc0, .umask=0x01);
|
||||
}
|
||||
|
||||
/*
|
||||
* The HSW11 requires a period larger than 100 which is the same as the BDM11.
|
||||
* A minimum period of 128 is enforced as well for the INST_RETIRED.ALL.
|
||||
*
|
||||
* The message 'interrupt took too long' can be observed on any counter which
|
||||
* was armed with a period < 32 and two events expired in the same NMI.
|
||||
* A minimum period of 32 is enforced for the rest of the events.
|
||||
*/
|
||||
static void hsw_limit_period(struct perf_event *event, s64 *left)
|
||||
{
|
||||
*left = max(*left, erratum_hsw11(event) ? 128 : 32);
|
||||
}
|
||||
|
||||
/*
|
||||
* Broadwell:
|
||||
*
|
||||
@ -4606,8 +4625,7 @@ static enum hybrid_cpu_type adl_get_hybrid_cpu_type(void)
|
||||
*/
|
||||
static void bdw_limit_period(struct perf_event *event, s64 *left)
|
||||
{
|
||||
if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
|
||||
X86_CONFIG(.event=0xc0, .umask=0x01)) {
|
||||
if (erratum_hsw11(event)) {
|
||||
if (*left < 128)
|
||||
*left = 128;
|
||||
*left &= ~0x3fULL;
|
||||
@ -6766,6 +6784,7 @@ __init int intel_pmu_init(void)
|
||||
|
||||
x86_pmu.hw_config = hsw_hw_config;
|
||||
x86_pmu.get_event_constraints = hsw_get_event_constraints;
|
||||
x86_pmu.limit_period = hsw_limit_period;
|
||||
x86_pmu.lbr_double_abort = true;
|
||||
extra_attr = boot_cpu_has(X86_FEATURE_RTM) ?
|
||||
hsw_format_attr : nhm_format_attr;
|
||||
|
@ -591,6 +591,13 @@ struct fpu_state_config {
|
||||
* even without XSAVE support, i.e. legacy features FP + SSE
|
||||
*/
|
||||
u64 legacy_features;
|
||||
/*
|
||||
* @independent_features:
|
||||
*
|
||||
* Features that are supported by XSAVES, but not managed as part of
|
||||
* the FPU core, such as LBR
|
||||
*/
|
||||
u64 independent_features;
|
||||
};
|
||||
|
||||
/* FPU state configuration information */
|
||||
|
@ -17,6 +17,7 @@ extern unsigned long phys_base;
|
||||
extern unsigned long page_offset_base;
|
||||
extern unsigned long vmalloc_base;
|
||||
extern unsigned long vmemmap_base;
|
||||
extern unsigned long physmem_end;
|
||||
|
||||
static __always_inline unsigned long __phys_addr_nodebug(unsigned long x)
|
||||
{
|
||||
|
@ -140,6 +140,10 @@ extern unsigned int ptrs_per_p4d;
|
||||
# define VMEMMAP_START __VMEMMAP_BASE_L4
|
||||
#endif /* CONFIG_DYNAMIC_MEMORY_LAYOUT */
|
||||
|
||||
#ifdef CONFIG_RANDOMIZE_MEMORY
|
||||
# define PHYSMEM_END physmem_end
|
||||
#endif
|
||||
|
||||
/*
|
||||
* End of the region for which vmalloc page tables are pre-allocated.
|
||||
* For non-KMSAN builds, this is the same as VMALLOC_END.
|
||||
|
@ -156,12 +156,6 @@ static inline void resctrl_sched_in(struct task_struct *tsk)
|
||||
__resctrl_sched_in(tsk);
|
||||
}
|
||||
|
||||
static inline u32 resctrl_arch_system_num_rmid_idx(void)
|
||||
{
|
||||
/* RMID are independent numbers for x86. num_rmid_idx == num_rmid */
|
||||
return boot_cpu_data.x86_cache_max_rmid + 1;
|
||||
}
|
||||
|
||||
static inline void resctrl_arch_rmid_idx_decode(u32 idx, u32 *closid, u32 *rmid)
|
||||
{
|
||||
*rmid = idx;
|
||||
|
@ -1775,12 +1775,9 @@ static __init void apic_set_fixmap(bool read_apic);
|
||||
|
||||
static __init void x2apic_disable(void)
|
||||
{
|
||||
u32 x2apic_id, state = x2apic_state;
|
||||
u32 x2apic_id;
|
||||
|
||||
x2apic_mode = 0;
|
||||
x2apic_state = X2APIC_DISABLED;
|
||||
|
||||
if (state != X2APIC_ON)
|
||||
if (x2apic_state < X2APIC_ON)
|
||||
return;
|
||||
|
||||
x2apic_id = read_apic_id();
|
||||
@ -1793,6 +1790,10 @@ static __init void x2apic_disable(void)
|
||||
}
|
||||
|
||||
__x2apic_disable();
|
||||
|
||||
x2apic_mode = 0;
|
||||
x2apic_state = X2APIC_DISABLED;
|
||||
|
||||
/*
|
||||
* Don't reread the APIC ID as it was already done from
|
||||
* check_x2apic() and the APIC driver still is a x2APIC variant,
|
||||
|
@ -119,6 +119,14 @@ struct rdt_hw_resource rdt_resources_all[] = {
|
||||
},
|
||||
};
|
||||
|
||||
u32 resctrl_arch_system_num_rmid_idx(void)
|
||||
{
|
||||
struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl;
|
||||
|
||||
/* RMID are independent numbers for x86. num_rmid_idx == num_rmid */
|
||||
return r->num_rmid;
|
||||
}
|
||||
|
||||
/*
|
||||
* cache_alloc_hsw_probe() - Have to probe for Intel haswell server CPUs
|
||||
* as they do not have CPUID enumeration support for Cache allocation.
|
||||
|
@ -788,6 +788,9 @@ void __init fpu__init_system_xstate(unsigned int legacy_size)
|
||||
goto out_disable;
|
||||
}
|
||||
|
||||
fpu_kernel_cfg.independent_features = fpu_kernel_cfg.max_features &
|
||||
XFEATURE_MASK_INDEPENDENT;
|
||||
|
||||
/*
|
||||
* Clear XSAVE features that are disabled in the normal CPUID.
|
||||
*/
|
||||
|
@ -62,9 +62,9 @@ static inline u64 xfeatures_mask_supervisor(void)
|
||||
static inline u64 xfeatures_mask_independent(void)
|
||||
{
|
||||
if (!cpu_feature_enabled(X86_FEATURE_ARCH_LBR))
|
||||
return XFEATURE_MASK_INDEPENDENT & ~XFEATURE_MASK_LBR;
|
||||
return fpu_kernel_cfg.independent_features & ~XFEATURE_MASK_LBR;
|
||||
|
||||
return XFEATURE_MASK_INDEPENDENT;
|
||||
return fpu_kernel_cfg.independent_features;
|
||||
}
|
||||
|
||||
/* XSAVE/XRSTOR wrapper functions */
|
||||
|
@ -19,7 +19,6 @@ if VIRTUALIZATION
|
||||
|
||||
config KVM
|
||||
tristate "Kernel-based Virtual Machine (KVM) support"
|
||||
depends on HIGH_RES_TIMERS
|
||||
depends on X86_LOCAL_APIC
|
||||
select KVM_COMMON
|
||||
select KVM_GENERIC_MMU_NOTIFIER
|
||||
@ -144,8 +143,10 @@ config KVM_AMD_SEV
|
||||
select HAVE_KVM_ARCH_GMEM_PREPARE
|
||||
select HAVE_KVM_ARCH_GMEM_INVALIDATE
|
||||
help
|
||||
Provides support for launching Encrypted VMs (SEV) and Encrypted VMs
|
||||
with Encrypted State (SEV-ES) on AMD processors.
|
||||
Provides support for launching encrypted VMs which use Secure
|
||||
Encrypted Virtualization (SEV), Secure Encrypted Virtualization with
|
||||
Encrypted State (SEV-ES), and Secure Encrypted Virtualization with
|
||||
Secure Nested Paging (SEV-SNP) technologies on AMD processors.
|
||||
|
||||
config KVM_SMM
|
||||
bool "System Management Mode emulation"
|
||||
|
@ -4750,7 +4750,9 @@ long kvm_arch_vcpu_pre_fault_memory(struct kvm_vcpu *vcpu,
|
||||
* reload is efficient when called repeatedly, so we can do it on
|
||||
* every iteration.
|
||||
*/
|
||||
kvm_mmu_reload(vcpu);
|
||||
r = kvm_mmu_reload(vcpu);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
if (kvm_arch_has_private_mem(vcpu->kvm) &&
|
||||
kvm_mem_is_private(vcpu->kvm, gpa_to_gfn(range->gpa)))
|
||||
|
@ -391,9 +391,9 @@ void kvm_mmu_set_mmio_spte_mask(u64 mmio_value, u64 mmio_mask, u64 access_mask)
|
||||
mmio_value = 0;
|
||||
|
||||
/*
|
||||
* The masked MMIO value must obviously match itself and a removed SPTE
|
||||
* must not get a false positive. Removed SPTEs and MMIO SPTEs should
|
||||
* never collide as MMIO must set some RWX bits, and removed SPTEs must
|
||||
* The masked MMIO value must obviously match itself and a frozen SPTE
|
||||
* must not get a false positive. Frozen SPTEs and MMIO SPTEs should
|
||||
* never collide as MMIO must set some RWX bits, and frozen SPTEs must
|
||||
* not set any RWX bits.
|
||||
*/
|
||||
if (WARN_ON((mmio_value & mmio_mask) != mmio_value) ||
|
||||
|
@ -214,7 +214,7 @@ extern u64 __read_mostly shadow_nonpresent_or_rsvd_mask;
|
||||
*/
|
||||
#define FROZEN_SPTE (SHADOW_NONPRESENT_VALUE | 0x5a0ULL)
|
||||
|
||||
/* Removed SPTEs must not be misconstrued as shadow present PTEs. */
|
||||
/* Frozen SPTEs must not be misconstrued as shadow present PTEs. */
|
||||
static_assert(!(FROZEN_SPTE & SPTE_MMU_PRESENT_MASK));
|
||||
|
||||
static inline bool is_frozen_spte(u64 spte)
|
||||
|
@ -359,10 +359,10 @@ static void handle_removed_pt(struct kvm *kvm, tdp_ptep_t pt, bool shared)
|
||||
/*
|
||||
* Set the SPTE to a nonpresent value that other
|
||||
* threads will not overwrite. If the SPTE was
|
||||
* already marked as removed then another thread
|
||||
* already marked as frozen then another thread
|
||||
* handling a page fault could overwrite it, so
|
||||
* set the SPTE until it is set from some other
|
||||
* value to the removed SPTE value.
|
||||
* value to the frozen SPTE value.
|
||||
*/
|
||||
for (;;) {
|
||||
old_spte = kvm_tdp_mmu_write_spte_atomic(sptep, FROZEN_SPTE);
|
||||
@ -536,8 +536,8 @@ static inline int __must_check __tdp_mmu_set_spte_atomic(struct tdp_iter *iter,
|
||||
u64 *sptep = rcu_dereference(iter->sptep);
|
||||
|
||||
/*
|
||||
* The caller is responsible for ensuring the old SPTE is not a REMOVED
|
||||
* SPTE. KVM should never attempt to zap or manipulate a REMOVED SPTE,
|
||||
* The caller is responsible for ensuring the old SPTE is not a FROZEN
|
||||
* SPTE. KVM should never attempt to zap or manipulate a FROZEN SPTE,
|
||||
* and pre-checking before inserting a new SPTE is advantageous as it
|
||||
* avoids unnecessary work.
|
||||
*/
|
||||
|
@ -2876,6 +2876,12 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
|
||||
case MSR_CSTAR:
|
||||
msr_info->data = svm->vmcb01.ptr->save.cstar;
|
||||
break;
|
||||
case MSR_GS_BASE:
|
||||
msr_info->data = svm->vmcb01.ptr->save.gs.base;
|
||||
break;
|
||||
case MSR_FS_BASE:
|
||||
msr_info->data = svm->vmcb01.ptr->save.fs.base;
|
||||
break;
|
||||
case MSR_KERNEL_GS_BASE:
|
||||
msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
|
||||
break;
|
||||
@ -3101,6 +3107,12 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
|
||||
case MSR_CSTAR:
|
||||
svm->vmcb01.ptr->save.cstar = data;
|
||||
break;
|
||||
case MSR_GS_BASE:
|
||||
svm->vmcb01.ptr->save.gs.base = data;
|
||||
break;
|
||||
case MSR_FS_BASE:
|
||||
svm->vmcb01.ptr->save.fs.base = data;
|
||||
break;
|
||||
case MSR_KERNEL_GS_BASE:
|
||||
svm->vmcb01.ptr->save.kernel_gs_base = data;
|
||||
break;
|
||||
@ -5224,6 +5236,9 @@ static __init void svm_set_cpu_caps(void)
|
||||
|
||||
/* CPUID 0x8000001F (SME/SEV features) */
|
||||
sev_set_cpu_caps();
|
||||
|
||||
/* Don't advertise Bus Lock Detect to guest if SVM support is absent */
|
||||
kvm_cpu_cap_clear(X86_FEATURE_BUS_LOCK_DETECT);
|
||||
}
|
||||
|
||||
static __init int svm_hardware_setup(void)
|
||||
|
@ -4656,7 +4656,6 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
|
||||
case KVM_CAP_ASYNC_PF_INT:
|
||||
case KVM_CAP_GET_TSC_KHZ:
|
||||
case KVM_CAP_KVMCLOCK_CTRL:
|
||||
case KVM_CAP_READONLY_MEM:
|
||||
case KVM_CAP_IOAPIC_POLARITY_IGNORED:
|
||||
case KVM_CAP_TSC_DEADLINE_TIMER:
|
||||
case KVM_CAP_DISABLE_QUIRKS:
|
||||
@ -4815,6 +4814,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
|
||||
case KVM_CAP_VM_TYPES:
|
||||
r = kvm_caps.supported_vm_types;
|
||||
break;
|
||||
case KVM_CAP_READONLY_MEM:
|
||||
r = kvm ? kvm_arch_has_readonly_mem(kvm) : 1;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@ -6040,7 +6042,9 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
|
||||
if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
|
||||
break;
|
||||
|
||||
kvm_vcpu_srcu_read_lock(vcpu);
|
||||
r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
|
||||
kvm_vcpu_srcu_read_unlock(vcpu);
|
||||
break;
|
||||
}
|
||||
case KVM_GET_DEBUGREGS: {
|
||||
|
@ -958,8 +958,12 @@ static void update_end_of_memory_vars(u64 start, u64 size)
|
||||
int add_pages(int nid, unsigned long start_pfn, unsigned long nr_pages,
|
||||
struct mhp_params *params)
|
||||
{
|
||||
unsigned long end = ((start_pfn + nr_pages) << PAGE_SHIFT) - 1;
|
||||
int ret;
|
||||
|
||||
if (WARN_ON_ONCE(end > PHYSMEM_END))
|
||||
return -ERANGE;
|
||||
|
||||
ret = __add_pages(nid, start_pfn, nr_pages, params);
|
||||
WARN_ON_ONCE(ret);
|
||||
|
||||
|
@ -47,13 +47,24 @@ static const unsigned long vaddr_end = CPU_ENTRY_AREA_BASE;
|
||||
*/
|
||||
static __initdata struct kaslr_memory_region {
|
||||
unsigned long *base;
|
||||
unsigned long *end;
|
||||
unsigned long size_tb;
|
||||
} kaslr_regions[] = {
|
||||
{ &page_offset_base, 0 },
|
||||
{ &vmalloc_base, 0 },
|
||||
{ &vmemmap_base, 0 },
|
||||
{
|
||||
.base = &page_offset_base,
|
||||
.end = &physmem_end,
|
||||
},
|
||||
{
|
||||
.base = &vmalloc_base,
|
||||
},
|
||||
{
|
||||
.base = &vmemmap_base,
|
||||
},
|
||||
};
|
||||
|
||||
/* The end of the possible address space for physical memory */
|
||||
unsigned long physmem_end __ro_after_init;
|
||||
|
||||
/* Get size in bytes used by the memory region */
|
||||
static inline unsigned long get_padding(struct kaslr_memory_region *region)
|
||||
{
|
||||
@ -82,6 +93,8 @@ void __init kernel_randomize_memory(void)
|
||||
BUILD_BUG_ON(vaddr_end != CPU_ENTRY_AREA_BASE);
|
||||
BUILD_BUG_ON(vaddr_end > __START_KERNEL_map);
|
||||
|
||||
/* Preset the end of the possible address space for physical memory */
|
||||
physmem_end = ((1ULL << MAX_PHYSMEM_BITS) - 1);
|
||||
if (!kaslr_memory_enabled())
|
||||
return;
|
||||
|
||||
@ -128,11 +141,18 @@ void __init kernel_randomize_memory(void)
|
||||
vaddr += entropy;
|
||||
*kaslr_regions[i].base = vaddr;
|
||||
|
||||
/*
|
||||
* Jump the region and add a minimum padding based on
|
||||
* randomization alignment.
|
||||
*/
|
||||
/* Calculate the end of the region */
|
||||
vaddr += get_padding(&kaslr_regions[i]);
|
||||
/*
|
||||
* KASLR trims the maximum possible size of the
|
||||
* direct-map. Update the physmem_end boundary.
|
||||
* No rounding required as the region starts
|
||||
* PUD aligned and size is in units of TB.
|
||||
*/
|
||||
if (kaslr_regions[i].end)
|
||||
*kaslr_regions[i].end = __pa_nodebug(vaddr - 1);
|
||||
|
||||
/* Add a minimum padding based on randomization alignment. */
|
||||
vaddr = round_up(vaddr + 1, PUD_SIZE);
|
||||
remain_entropy -= entropy;
|
||||
}
|
||||
|
@ -167,10 +167,6 @@ int bio_integrity_add_page(struct bio *bio, struct page *page,
|
||||
struct request_queue *q = bdev_get_queue(bio->bi_bdev);
|
||||
struct bio_integrity_payload *bip = bio_integrity(bio);
|
||||
|
||||
if (((bip->bip_iter.bi_size + len) >> SECTOR_SHIFT) >
|
||||
queue_max_hw_sectors(q))
|
||||
return 0;
|
||||
|
||||
if (bip->bip_vcnt > 0) {
|
||||
struct bio_vec *bv = &bip->bip_vec[bip->bip_vcnt - 1];
|
||||
bool same_page = false;
|
||||
|
@ -174,7 +174,7 @@ static int blkdev_issue_write_zeroes(struct block_device *bdev, sector_t sector,
|
||||
* on an I/O error, in which case we'll turn any error into
|
||||
* "not supported" here.
|
||||
*/
|
||||
if (ret && !limit)
|
||||
if (ret && !bdev_write_zeroes_sectors(bdev))
|
||||
return -EOPNOTSUPP;
|
||||
return ret;
|
||||
}
|
||||
|
@ -3422,6 +3422,7 @@ static void binder_transaction(struct binder_proc *proc,
|
||||
*/
|
||||
copy_size = object_offset - user_offset;
|
||||
if (copy_size && (user_offset > object_offset ||
|
||||
object_offset > tr->data_size ||
|
||||
binder_alloc_copy_user_to_buffer(
|
||||
&target_proc->alloc,
|
||||
t->buffer, user_offset,
|
||||
|
@ -5593,8 +5593,10 @@ struct ata_host *ata_host_alloc(struct device *dev, int n_ports)
|
||||
}
|
||||
|
||||
dr = devres_alloc(ata_devres_release, 0, GFP_KERNEL);
|
||||
if (!dr)
|
||||
if (!dr) {
|
||||
kfree(host);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
devres_add(dev, dr);
|
||||
dev_set_drvdata(dev, host);
|
||||
|
@ -2663,6 +2663,8 @@ static int ublk_ctrl_start_recovery(struct ublk_device *ub,
|
||||
mutex_lock(&ub->mutex);
|
||||
if (!ublk_can_use_recovery(ub))
|
||||
goto out_unlock;
|
||||
if (!ub->nr_queues_ready)
|
||||
goto out_unlock;
|
||||
/*
|
||||
* START_RECOVERY is only allowd after:
|
||||
*
|
||||
|
@ -12,6 +12,7 @@
|
||||
#include <linux/acpi.h>
|
||||
#include <acpi/acpi_bus.h>
|
||||
#include <asm/unaligned.h>
|
||||
#include <linux/efi.h>
|
||||
|
||||
#include <net/bluetooth/bluetooth.h>
|
||||
#include <net/bluetooth/hci_core.h>
|
||||
@ -26,6 +27,8 @@
|
||||
#define ECDSA_OFFSET 644
|
||||
#define ECDSA_HEADER_LEN 320
|
||||
|
||||
#define BTINTEL_EFI_DSBR L"UefiCnvCommonDSBR"
|
||||
|
||||
enum {
|
||||
DSM_SET_WDISABLE2_DELAY = 1,
|
||||
DSM_SET_RESET_METHOD = 3,
|
||||
@ -2616,6 +2619,120 @@ static u8 btintel_classify_pkt_type(struct hci_dev *hdev, struct sk_buff *skb)
|
||||
return hci_skb_pkt_type(skb);
|
||||
}
|
||||
|
||||
/*
|
||||
* UefiCnvCommonDSBR UEFI variable provides information from the OEM platforms
|
||||
* if they have replaced the BRI (Bluetooth Radio Interface) resistor to
|
||||
* overcome the potential STEP errors on their designs. Based on the
|
||||
* configauration, bluetooth firmware shall adjust the BRI response line drive
|
||||
* strength. The below structure represents DSBR data.
|
||||
* struct {
|
||||
* u8 header;
|
||||
* u32 dsbr;
|
||||
* } __packed;
|
||||
*
|
||||
* header - defines revision number of the structure
|
||||
* dsbr - defines drive strength BRI response
|
||||
* bit0
|
||||
* 0 - instructs bluetooth firmware to use default values
|
||||
* 1 - instructs bluetooth firmware to override default values
|
||||
* bit3:1
|
||||
* Reserved
|
||||
* bit7:4
|
||||
* DSBR override values (only if bit0 is set. Default value is 0xF
|
||||
* bit31:7
|
||||
* Reserved
|
||||
* Expected values for dsbr field:
|
||||
* 1. 0xF1 - indicates that the resistor on board is 33 Ohm
|
||||
* 2. 0x00 or 0xB1 - indicates that the resistor on board is 10 Ohm
|
||||
* 3. Non existing UEFI variable or invalid (none of the above) - indicates
|
||||
* that the resistor on board is 10 Ohm
|
||||
* Even if uefi variable is not present, driver shall send 0xfc0a command to
|
||||
* firmware to use default values.
|
||||
*
|
||||
*/
|
||||
static int btintel_uefi_get_dsbr(u32 *dsbr_var)
|
||||
{
|
||||
struct btintel_dsbr {
|
||||
u8 header;
|
||||
u32 dsbr;
|
||||
} __packed data;
|
||||
|
||||
efi_status_t status;
|
||||
unsigned long data_size = 0;
|
||||
efi_guid_t guid = EFI_GUID(0xe65d8884, 0xd4af, 0x4b20, 0x8d, 0x03,
|
||||
0x77, 0x2e, 0xcc, 0x3d, 0xa5, 0x31);
|
||||
|
||||
if (!IS_ENABLED(CONFIG_EFI))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
if (!efi_rt_services_supported(EFI_RT_SUPPORTED_GET_VARIABLE))
|
||||
return -EOPNOTSUPP;
|
||||
|
||||
status = efi.get_variable(BTINTEL_EFI_DSBR, &guid, NULL, &data_size,
|
||||
NULL);
|
||||
|
||||
if (status != EFI_BUFFER_TOO_SMALL || !data_size)
|
||||
return -EIO;
|
||||
|
||||
status = efi.get_variable(BTINTEL_EFI_DSBR, &guid, NULL, &data_size,
|
||||
&data);
|
||||
|
||||
if (status != EFI_SUCCESS)
|
||||
return -ENXIO;
|
||||
|
||||
*dsbr_var = data.dsbr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int btintel_set_dsbr(struct hci_dev *hdev, struct intel_version_tlv *ver)
|
||||
{
|
||||
struct btintel_dsbr_cmd {
|
||||
u8 enable;
|
||||
u8 dsbr;
|
||||
} __packed;
|
||||
|
||||
struct btintel_dsbr_cmd cmd;
|
||||
struct sk_buff *skb;
|
||||
u8 status;
|
||||
u32 dsbr;
|
||||
bool apply_dsbr;
|
||||
int err;
|
||||
|
||||
/* DSBR command needs to be sent for BlazarI + B0 step product after
|
||||
* downloading IML image.
|
||||
*/
|
||||
apply_dsbr = (ver->img_type == BTINTEL_IMG_IML &&
|
||||
((ver->cnvi_top & 0xfff) == BTINTEL_CNVI_BLAZARI) &&
|
||||
INTEL_CNVX_TOP_STEP(ver->cnvi_top) == 0x01);
|
||||
|
||||
if (!apply_dsbr)
|
||||
return 0;
|
||||
|
||||
dsbr = 0;
|
||||
err = btintel_uefi_get_dsbr(&dsbr);
|
||||
if (err < 0)
|
||||
bt_dev_dbg(hdev, "Error reading efi: %ls (%d)",
|
||||
BTINTEL_EFI_DSBR, err);
|
||||
|
||||
cmd.enable = dsbr & BIT(0);
|
||||
cmd.dsbr = dsbr >> 4 & 0xF;
|
||||
|
||||
bt_dev_info(hdev, "dsbr: enable: 0x%2.2x value: 0x%2.2x", cmd.enable,
|
||||
cmd.dsbr);
|
||||
|
||||
skb = __hci_cmd_sync(hdev, 0xfc0a, sizeof(cmd), &cmd, HCI_CMD_TIMEOUT);
|
||||
if (IS_ERR(skb))
|
||||
return -bt_to_errno(PTR_ERR(skb));
|
||||
|
||||
status = skb->data[0];
|
||||
kfree_skb(skb);
|
||||
|
||||
if (status)
|
||||
return -bt_to_errno(status);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int btintel_bootloader_setup_tlv(struct hci_dev *hdev,
|
||||
struct intel_version_tlv *ver)
|
||||
{
|
||||
@ -2650,6 +2767,13 @@ int btintel_bootloader_setup_tlv(struct hci_dev *hdev,
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* set drive strength of BRI response */
|
||||
err = btintel_set_dsbr(hdev, ver);
|
||||
if (err) {
|
||||
bt_dev_err(hdev, "Failed to send dsbr command (%d)", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
/* If image type returned is BTINTEL_IMG_IML, then controller supports
|
||||
* intermediate loader image
|
||||
*/
|
||||
|
@ -449,6 +449,23 @@ static bool ps_wakeup(struct btnxpuart_dev *nxpdev)
|
||||
return false;
|
||||
}
|
||||
|
||||
static void ps_cleanup(struct btnxpuart_dev *nxpdev)
|
||||
{
|
||||
struct ps_data *psdata = &nxpdev->psdata;
|
||||
u8 ps_state;
|
||||
|
||||
mutex_lock(&psdata->ps_lock);
|
||||
ps_state = psdata->ps_state;
|
||||
mutex_unlock(&psdata->ps_lock);
|
||||
|
||||
if (ps_state != PS_STATE_AWAKE)
|
||||
ps_control(psdata->hdev, PS_STATE_AWAKE);
|
||||
|
||||
ps_cancel_timer(nxpdev);
|
||||
cancel_work_sync(&psdata->work);
|
||||
mutex_destroy(&psdata->ps_lock);
|
||||
}
|
||||
|
||||
static int send_ps_cmd(struct hci_dev *hdev, void *data)
|
||||
{
|
||||
struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev);
|
||||
@ -1363,7 +1380,6 @@ static int btnxpuart_close(struct hci_dev *hdev)
|
||||
{
|
||||
struct btnxpuart_dev *nxpdev = hci_get_drvdata(hdev);
|
||||
|
||||
ps_wakeup(nxpdev);
|
||||
serdev_device_close(nxpdev->serdev);
|
||||
skb_queue_purge(&nxpdev->txq);
|
||||
if (!IS_ERR_OR_NULL(nxpdev->rx_skb)) {
|
||||
@ -1516,8 +1532,8 @@ static void nxp_serdev_remove(struct serdev_device *serdev)
|
||||
nxpdev->new_baudrate = nxpdev->fw_init_baudrate;
|
||||
nxp_set_baudrate_cmd(hdev, NULL);
|
||||
}
|
||||
ps_cancel_timer(nxpdev);
|
||||
}
|
||||
ps_cleanup(nxpdev);
|
||||
hci_unregister_dev(hdev);
|
||||
hci_free_dev(hdev);
|
||||
}
|
||||
|
@ -1091,6 +1091,7 @@ static void qca_controller_memdump(struct work_struct *work)
|
||||
qca->memdump_state = QCA_MEMDUMP_COLLECTED;
|
||||
cancel_delayed_work(&qca->ctrl_memdump_timeout);
|
||||
clear_bit(QCA_MEMDUMP_COLLECTION, &qca->flags);
|
||||
clear_bit(QCA_IBS_DISABLED, &qca->flags);
|
||||
mutex_unlock(&qca->hci_memdump_lock);
|
||||
return;
|
||||
}
|
||||
|
@ -698,6 +698,10 @@ static int tpm_ibmvtpm_probe(struct vio_dev *vio_dev,
|
||||
rc = tpm2_get_cc_attrs_tbl(chip);
|
||||
if (rc)
|
||||
goto init_irq_cleanup;
|
||||
|
||||
rc = tpm2_sessions_init(chip);
|
||||
if (rc)
|
||||
goto init_irq_cleanup;
|
||||
}
|
||||
|
||||
return tpm_chip_register(chip);
|
||||
|
@ -40,7 +40,8 @@
|
||||
|
||||
#define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL])
|
||||
# define PLL_POST_DIV_SHIFT 8
|
||||
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width, 0)
|
||||
# define PLL_POST_DIV_MASK(p) GENMASK((p)->width - 1, 0)
|
||||
# define PLL_ALPHA_MSB BIT(15)
|
||||
# define PLL_ALPHA_EN BIT(24)
|
||||
# define PLL_ALPHA_MODE BIT(25)
|
||||
# define PLL_VCO_SHIFT 20
|
||||
@ -1552,8 +1553,8 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
}
|
||||
|
||||
return regmap_update_bits(regmap, PLL_USER_CTL(pll),
|
||||
PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT,
|
||||
val << PLL_POST_DIV_SHIFT);
|
||||
PLL_POST_DIV_MASK(pll) << pll->post_div_shift,
|
||||
val << pll->post_div_shift);
|
||||
}
|
||||
|
||||
const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
|
||||
@ -2117,6 +2118,18 @@ static void clk_zonda_pll_disable(struct clk_hw *hw)
|
||||
regmap_write(regmap, PLL_OPMODE(pll), 0x0);
|
||||
}
|
||||
|
||||
static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l)
|
||||
{
|
||||
u64 remainder, quotient;
|
||||
|
||||
quotient = rate;
|
||||
remainder = do_div(quotient, prate);
|
||||
*l = quotient;
|
||||
|
||||
if ((remainder * 2) / prate)
|
||||
*l = *l + 1;
|
||||
}
|
||||
|
||||
static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long prate)
|
||||
{
|
||||
@ -2133,9 +2146,15 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
if (a & PLL_ALPHA_MSB)
|
||||
zonda_pll_adjust_l_val(rate, prate, &l);
|
||||
|
||||
regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
|
||||
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
|
||||
|
||||
if (!clk_hw_is_enabled(hw))
|
||||
return 0;
|
||||
|
||||
/* Wait before polling for the frequency latch */
|
||||
udelay(5);
|
||||
|
||||
|
@ -198,6 +198,7 @@ extern const struct clk_ops clk_byte2_ops;
|
||||
extern const struct clk_ops clk_pixel_ops;
|
||||
extern const struct clk_ops clk_gfx3d_ops;
|
||||
extern const struct clk_ops clk_rcg2_shared_ops;
|
||||
extern const struct clk_ops clk_rcg2_shared_no_init_park_ops;
|
||||
extern const struct clk_ops clk_dp_ops;
|
||||
|
||||
struct clk_rcg_dfs_data {
|
||||
|
@ -1348,6 +1348,36 @@ const struct clk_ops clk_rcg2_shared_ops = {
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
|
||||
|
||||
static int clk_rcg2_shared_no_init_park(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
|
||||
|
||||
/*
|
||||
* Read the config register so that the parent is properly mapped at
|
||||
* registration time.
|
||||
*/
|
||||
regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &rcg->parked_cfg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Like clk_rcg2_shared_ops but skip the init so that the clk frequency is left
|
||||
* unchanged at registration time.
|
||||
*/
|
||||
const struct clk_ops clk_rcg2_shared_no_init_park_ops = {
|
||||
.init = clk_rcg2_shared_no_init_park,
|
||||
.enable = clk_rcg2_shared_enable,
|
||||
.disable = clk_rcg2_shared_disable,
|
||||
.get_parent = clk_rcg2_shared_get_parent,
|
||||
.set_parent = clk_rcg2_shared_set_parent,
|
||||
.recalc_rate = clk_rcg2_shared_recalc_rate,
|
||||
.determine_rate = clk_rcg2_determine_rate,
|
||||
.set_rate = clk_rcg2_shared_set_rate,
|
||||
.set_rate_and_parent = clk_rcg2_shared_set_rate_and_parent,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_rcg2_shared_no_init_park_ops);
|
||||
|
||||
/* Common APIs to be used for DFS based RCGR */
|
||||
static void clk_rcg2_dfs_populate_freq(struct clk_hw *hw, unsigned int l,
|
||||
struct freq_tbl *f)
|
||||
|
@ -68,7 +68,7 @@ static const struct clk_parent_data gcc_sleep_clk_data[] = {
|
||||
|
||||
static struct clk_alpha_pll gpll0_main = {
|
||||
.offset = 0x20000,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
|
||||
.clkr = {
|
||||
.enable_reg = 0x0b000,
|
||||
.enable_mask = BIT(0),
|
||||
@ -96,7 +96,7 @@ static struct clk_fixed_factor gpll0_out_main_div2 = {
|
||||
|
||||
static struct clk_alpha_pll_postdiv gpll0 = {
|
||||
.offset = 0x20000,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpll0",
|
||||
@ -110,7 +110,7 @@ static struct clk_alpha_pll_postdiv gpll0 = {
|
||||
|
||||
static struct clk_alpha_pll gpll4_main = {
|
||||
.offset = 0x22000,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
|
||||
.clkr = {
|
||||
.enable_reg = 0x0b000,
|
||||
.enable_mask = BIT(2),
|
||||
@ -125,7 +125,7 @@ static struct clk_alpha_pll gpll4_main = {
|
||||
|
||||
static struct clk_alpha_pll_postdiv gpll4 = {
|
||||
.offset = 0x22000,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpll4",
|
||||
@ -139,7 +139,7 @@ static struct clk_alpha_pll_postdiv gpll4 = {
|
||||
|
||||
static struct clk_alpha_pll gpll2_main = {
|
||||
.offset = 0x21000,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
|
||||
.clkr = {
|
||||
.enable_reg = 0x0b000,
|
||||
.enable_mask = BIT(1),
|
||||
@ -154,7 +154,7 @@ static struct clk_alpha_pll gpll2_main = {
|
||||
|
||||
static struct clk_alpha_pll_postdiv gpll2 = {
|
||||
.offset = 0x21000,
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
|
||||
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT_EVO],
|
||||
.width = 4,
|
||||
.clkr.hw.init = &(const struct clk_init_data) {
|
||||
.name = "gpll2",
|
||||
|
@ -1500,7 +1500,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
|
||||
@ -1517,7 +1517,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
|
||||
@ -1534,7 +1534,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
|
||||
@ -1551,7 +1551,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
|
||||
@ -1568,7 +1568,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
|
||||
@ -1585,7 +1585,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
|
||||
@ -1617,7 +1617,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
|
||||
@ -1634,7 +1634,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
|
||||
@ -1651,7 +1651,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
@ -1668,7 +1668,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
@ -1685,7 +1685,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
|
||||
@ -1702,7 +1702,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
@ -1719,7 +1719,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
@ -1736,7 +1736,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
@ -1753,7 +1753,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
||||
@ -1770,7 +1770,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
|
||||
@ -1787,7 +1787,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
@ -1804,7 +1804,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
@ -1821,7 +1821,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
@ -1838,7 +1838,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
@ -1855,7 +1855,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
@ -1872,7 +1872,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
@ -1889,7 +1889,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
||||
@ -1906,7 +1906,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
|
||||
|
@ -536,7 +536,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -551,7 +551,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -566,7 +566,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -581,7 +581,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -596,7 +596,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -611,7 +611,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -626,7 +626,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -641,7 +641,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -656,7 +656,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -671,7 +671,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -700,7 +700,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
@ -717,7 +717,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
@ -750,7 +750,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
|
||||
@ -767,7 +767,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
@ -784,7 +784,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
@ -801,7 +801,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
@ -818,7 +818,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
||||
@ -835,7 +835,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
|
||||
@ -852,7 +852,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
@ -869,7 +869,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
@ -886,7 +886,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
@ -903,7 +903,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
@ -920,7 +920,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
@ -937,7 +937,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
@ -975,7 +975,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_8,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
||||
@ -992,7 +992,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
|
||||
@ -1159,7 +1159,7 @@ static struct clk_rcg2 gcc_usb30_prim_master_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_shared_no_init_park_ops,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -713,7 +713,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s0_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -728,7 +728,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s1_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -743,7 +743,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s2_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -758,7 +758,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s3_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -773,7 +773,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s4_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -788,7 +788,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s5_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -803,7 +803,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s6_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -818,7 +818,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s7_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -833,7 +833,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s8_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -848,7 +848,7 @@ static struct clk_rcg2 gcc_qupv3_i2c_s9_clk_src = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -863,7 +863,7 @@ static struct clk_init_data gcc_qupv3_wrap1_qspi_ref_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_qspi_ref_clk_src = {
|
||||
@ -899,7 +899,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
@ -916,7 +916,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
@ -948,7 +948,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
@ -980,7 +980,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
@ -997,7 +997,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
@ -1014,7 +1014,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
||||
@ -1031,7 +1031,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
|
||||
@ -1059,7 +1059,7 @@ static struct clk_rcg2 gcc_qupv3_wrap2_ibi_ctrl_0_clk_src = {
|
||||
.parent_data = gcc_parent_data_2,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_2),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
},
|
||||
};
|
||||
|
||||
@ -1068,7 +1068,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
@ -1085,7 +1085,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
@ -1102,7 +1102,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
@ -1119,7 +1119,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
@ -1136,7 +1136,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
@ -1153,7 +1153,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
@ -1186,7 +1186,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_10,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_10),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
||||
@ -1203,7 +1203,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
|
||||
@ -1226,7 +1226,7 @@ static struct clk_init_data gcc_qupv3_wrap3_qspi_ref_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap3_qspi_ref_clk_src = {
|
||||
|
@ -670,7 +670,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s0_clk_src = {
|
||||
@ -687,7 +687,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s1_clk_src = {
|
||||
@ -719,7 +719,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s2_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s2_clk_src = {
|
||||
@ -736,7 +736,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s3_clk_src = {
|
||||
@ -768,7 +768,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s4_clk_src = {
|
||||
@ -785,7 +785,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s5_clk_src = {
|
||||
@ -802,7 +802,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s6_clk_src = {
|
||||
@ -819,7 +819,7 @@ static struct clk_init_data gcc_qupv3_wrap0_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap0_s7_clk_src = {
|
||||
@ -836,7 +836,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s0_clk_src = {
|
||||
@ -853,7 +853,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s1_clk_src = {
|
||||
@ -870,7 +870,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s2_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s2_clk_src = {
|
||||
@ -887,7 +887,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s3_clk_src = {
|
||||
@ -904,7 +904,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s4_clk_src = {
|
||||
@ -921,7 +921,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s5_clk_src = {
|
||||
@ -938,7 +938,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s6_clk_src = {
|
||||
@ -955,7 +955,7 @@ static struct clk_init_data gcc_qupv3_wrap1_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap1_s7_clk_src = {
|
||||
@ -972,7 +972,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s0_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s0_clk_src = {
|
||||
@ -989,7 +989,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s1_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s1_clk_src = {
|
||||
@ -1006,7 +1006,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s2_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s2_clk_src = {
|
||||
@ -1023,7 +1023,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s3_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s3_clk_src = {
|
||||
@ -1040,7 +1040,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s4_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s4_clk_src = {
|
||||
@ -1057,7 +1057,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s5_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s5_clk_src = {
|
||||
@ -1074,7 +1074,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s6_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_8,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_8),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
|
||||
@ -1091,7 +1091,7 @@ static struct clk_init_data gcc_qupv3_wrap2_s7_clk_src_init = {
|
||||
.parent_data = gcc_parent_data_0,
|
||||
.num_parents = ARRAY_SIZE(gcc_parent_data_0),
|
||||
.flags = CLK_SET_RATE_PARENT,
|
||||
.ops = &clk_rcg2_shared_ops,
|
||||
.ops = &clk_rcg2_ops,
|
||||
};
|
||||
|
||||
static struct clk_rcg2 gcc_qupv3_wrap2_s7_clk_src = {
|
||||
@ -6203,7 +6203,7 @@ static struct gdsc gcc_usb_0_phy_gdsc = {
|
||||
.pd = {
|
||||
.name = "gcc_usb_0_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
@ -6215,7 +6215,7 @@ static struct gdsc gcc_usb_1_phy_gdsc = {
|
||||
.pd = {
|
||||
.name = "gcc_usb_1_phy_gdsc",
|
||||
},
|
||||
.pwrsts = PWRSTS_OFF_ON,
|
||||
.pwrsts = PWRSTS_RET_ON,
|
||||
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
||||
};
|
||||
|
||||
|
@ -385,6 +385,32 @@ int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
|
||||
|
||||
/*
|
||||
* This clock notifier is called when the rate of PLL0 clock is to be changed.
|
||||
* The cpu_root clock should save the curent parent clock and switch its parent
|
||||
* clock to osc before PLL0 rate will be changed. Then switch its parent clock
|
||||
* back after the PLL0 rate is completed.
|
||||
*/
|
||||
static int jh7110_pll0_clk_notifier_cb(struct notifier_block *nb,
|
||||
unsigned long action, void *data)
|
||||
{
|
||||
struct jh71x0_clk_priv *priv = container_of(nb, struct jh71x0_clk_priv, pll_clk_nb);
|
||||
struct clk *cpu_root = priv->reg[JH7110_SYSCLK_CPU_ROOT].hw.clk;
|
||||
int ret = 0;
|
||||
|
||||
if (action == PRE_RATE_CHANGE) {
|
||||
struct clk *osc = clk_get(priv->dev, "osc");
|
||||
|
||||
priv->original_clk = clk_get_parent(cpu_root);
|
||||
ret = clk_set_parent(cpu_root, osc);
|
||||
clk_put(osc);
|
||||
} else if (action == POST_RATE_CHANGE) {
|
||||
ret = clk_set_parent(cpu_root, priv->original_clk);
|
||||
}
|
||||
|
||||
return notifier_from_errno(ret);
|
||||
}
|
||||
|
||||
static int __init jh7110_syscrg_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct jh71x0_clk_priv *priv;
|
||||
@ -413,7 +439,10 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(priv->pll[0]))
|
||||
return PTR_ERR(priv->pll[0]);
|
||||
} else {
|
||||
clk_put(pllclk);
|
||||
priv->pll_clk_nb.notifier_call = jh7110_pll0_clk_notifier_cb;
|
||||
ret = clk_notifier_register(pllclk, &priv->pll_clk_nb);
|
||||
if (ret)
|
||||
return ret;
|
||||
priv->pll[0] = NULL;
|
||||
}
|
||||
|
||||
|
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Reference in New Issue
Block a user