PCI: mvebu: move clock enable before register access

The clock passed to PCI controller found on MVEBU SoCs may come from a
clock gate. This requires the clock to be enabled before any registers
are accessed. Therefore, move the clock enable before register iomap to
ensure it is enabled.

Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Sebastian Hesselbarth 2013-08-13 14:25:20 +02:00 committed by Jason Cooper
parent 5b4deb6526
commit b42285f66f

View File

@ -897,11 +897,23 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
continue;
}
port->clk = of_clk_get_by_name(child, NULL);
if (IS_ERR(port->clk)) {
dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
port->port, port->lane);
continue;
}
ret = clk_prepare_enable(port->clk);
if (ret)
continue;
port->base = mvebu_pcie_map_registers(pdev, child, port);
if (IS_ERR(port->base)) {
dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
port->port, port->lane);
port->base = NULL;
clk_disable_unprepare(port->clk);
continue;
}
@ -917,22 +929,9 @@ static int __init mvebu_pcie_probe(struct platform_device *pdev)
port->port, port->lane);
}
port->clk = of_clk_get_by_name(child, NULL);
if (IS_ERR(port->clk)) {
dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
port->port, port->lane);
iounmap(port->base);
port->haslink = 0;
continue;
}
port->dn = child;
clk_prepare_enable(port->clk);
spin_lock_init(&port->conf_lock);
mvebu_sw_pci_bridge_init(port);
i++;
}