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ARM: dts: imx6q-bx50v3: Enable i2c recovery mechanism
This commit enables i2c recovery, supported by the i2c core subsystem. It defines the required GPIOs for SDA and SCL lines. Signed-off-by: Jose Alarcon <jose.alarcon@ge.com> Signed-off-by: Nandor Han <nandor.han@ge.com> Signed-off-by: Romain Perier <romain.perier@collabora.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -111,6 +111,11 @@
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};
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&i2c1 {
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pinctrl-names = "default", "gpio";
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
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scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
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pca9547: mux@70 {
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compatible = "nxp,pca9547";
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reg = <0x70>;
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@ -261,6 +266,43 @@
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};
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};
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&i2c2 {
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pinctrl-names = "default", "gpio";
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
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scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
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};
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&i2c3 {
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pinctrl-names = "default", "gpio";
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pinctrl-1 = <&pinctrl_i2c3_gpio>;
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sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
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scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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};
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&iomuxc {
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pinctrl_i2c1_gpio: i2c1gpiogrp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x1b0b0
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MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x1b0b0
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>;
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};
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pinctrl_i2c2_gpio: i2c2gpiogrp {
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fsl,pins = <
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MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0
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MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0
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>;
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};
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pinctrl_i2c3_gpio: i2c3gpiogrp {
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fsl,pins = <
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MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
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MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
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>;
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};
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};
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&usdhc4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc4>;
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