mirror of
https://github.com/torvalds/linux.git
synced 2024-11-29 07:31:29 +00:00
Add PowerVR Series5 SGX GPUs for the TI SoCs
With the Imagination Rogue GPU binding added, let's also add the devicetree binding for earlier SGX GPUs. Let's also patch the TI SoCs for the related SGX GPU nodes. Based on the mailing list discussions, the conclusion was that we need two separate device tree bindings, one for Rogue and upcoming GPUS, and one for the older SGX GPUs. For merging the changes, I applied the binding changes together with the TI SoC related changes into a branch leaving out the sun6i and mips changes as suggested by Rob. These changes are mostly 32-bit SoCs, but also contains one arm64 change. It does not cause any merge conflicts. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAmXcZiwRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXNyoBAAgI4qgIZWMNuccDnSwn+UCTDySqa+EBCK l7M9jrrLJ8Z+8Wz498lGp6hMD+3fa1bUHYmf8WE9+hWvUL4YcTpAxueTMJ8lvQE0 b6SM85G08p8Golm+PNXjz+JrJed83bfjZeZQJZqYZsrRyS8fw1Q/dpilydZhURpR gm8Sh7V1Q1FXHyh/j3C4Yo5m048bG50PmAp3Cqw8Pu5UvW+mNPMFc+3c06O6wtWy jgNb6JiNFkRlNkpnnx+JTjXaZcrsB2k1uodOMYBJjc8fndRlhKPuNYvA9ZEAhgQU W4L4BL/uJODciRY9yIciB8Qn5ulsjTJOW+pwQfhRnPAjf4h5/Dw68GJLLtBAtSbt 2Kt2t+Ma1CBDxumvCpj6FK48rmCKeF3i+HVbgQyqMjh3izDvXLlMCaDXuw5ema3j 7ihNEw+am0Upy84meT4qzksX73QnVF/3reWGnH97I+fpxW/ec4UcjeU1zEJvSwZ1 +GwEzl4eufFyBph70pJrU7RUpI52kMm8gdM3Wlcr4I+IkSQITx8pm0ed+l4lKJTI YFCZq9RZaf8uGPIi6fUXBeZOHjEJRVpqyrMIBI8Vb4KZAMk8tj1o0UjmxLiU2pLF tOzd0s/LJrsKOCDDXWVxk2Y33L+mPm65LV0U3ZJA3k3BVi8k+n/FGqxaSIKmrsEd eWjzriVh43w= =4Z+H -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmXhzNQACgkQYKtH/8kJ UicMlBAA1NuNlFF56ckjDUWXLtL2oQlS/0Wi1uiqCJ6SjvGgly5STBOgLphKfZr2 tdv43qJf9c8lfseZR6KzEirjc21Lk615jJkXq5Qh6P9FnhvyL6WfZ0XvKkSYZ06e sFCfLuFeehaR0i7gN0hFq+4tybotoJS29iu5HYPcDuD+dsNn71B73TmhzWvo6bSd ELCjftUkgZWPxHsG+oSDrhmuGSYLCSaDAmJvhCE8hwHLQ7b4ukwGHHu3iLGHJN+e vgyviRCYiknGSS1T6I5OHZWUySu3fExexpxtUkSlMsnkDXqGExjD/nanKeQ3nQJp ilmJ7jxS/or3Y28PYwDWwRX715FkoBfrPlzNDAFW4QVTNxspYbL1akhdnafofvC2 ehSpCHW4C8FR04Ias4ofzPPDAPTEzszxpeFHJcYdfSpIv48PHOkHgRuQta0iv8S7 jP46Q4hMUf+8qZT3MArmN9IjcSW3zVJDO4alWPmBRwUjOQw8vXSx3XrzHQF0Ivmb J6AGb/higgCSMrYBBhsnpbXmbBCems/mh4IO/6Ni5hWoX86Qj4Hz1+8qbG5A4aeL HM0lujl0ufnHNzIJKlsE/mJhE20fQgHsEkkRDpexDtyYq7B1Vmjx7pJweZyiss67 j0yWw/6RvUfe/17XI33r2qqtiwr2fZfg2PNPIV1Dr0qXQftB/PA= =PpqJ -----END PGP SIGNATURE----- Merge tag 'sgx-for-v6.9-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into soc/dt Add PowerVR Series5 SGX GPUs for the TI SoCs With the Imagination Rogue GPU binding added, let's also add the devicetree binding for earlier SGX GPUs. Let's also patch the TI SoCs for the related SGX GPU nodes. Based on the mailing list discussions, the conclusion was that we need two separate device tree bindings, one for Rogue and upcoming GPUS, and one for the older SGX GPUs. For merging the changes, I applied the binding changes together with the TI SoC related changes into a branch leaving out the sun6i and mips changes as suggested by Rob. These changes are mostly 32-bit SoCs, but also contains one arm64 change. It does not cause any merge conflicts. * tag 'sgx-for-v6.9-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: arm64: dts: ti: k3-am654-main: Add device tree entry for SGX GPU ARM: dts: DRA7xx: Add device tree entry for SGX GPU ARM: dts: AM437x: Add device tree entry for SGX GPU ARM: dts: AM33xx: Add device tree entry for SGX GPU ARM: dts: omap5: Add device tree entry for SGX GPU ARM: dts: omap4: Add device tree entry for SGX GPU ARM: dts: omap3: Add device tree entry for SGX GPU dt-bindings: gpu: Add PowerVR Series5 SGX GPUs dt-bindings: gpu: Rename img,powervr to img,powervr-rogue Link: https://lore.kernel.org/r/pull-1708943489-872615@atomide.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
b339605081
@ -2,10 +2,10 @@
|
||||
# Copyright (c) 2023 Imagination Technologies Ltd.
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpu/img,powervr.yaml#
|
||||
$id: http://devicetree.org/schemas/gpu/img,powervr-rogue.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Imagination Technologies PowerVR and IMG GPU
|
||||
title: Imagination Technologies PowerVR and IMG Rogue GPUs
|
||||
|
||||
maintainers:
|
||||
- Frank Binns <frank.binns@imgtec.com>
|
138
Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
Normal file
138
Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
Normal file
@ -0,0 +1,138 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
# Copyright (c) 2023 Imagination Technologies Ltd.
|
||||
# Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/gpu/img,powervr-sgx.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Imagination Technologies PowerVR SGX GPUs
|
||||
|
||||
maintainers:
|
||||
- Frank Binns <frank.binns@imgtec.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- ti,omap3430-gpu # Rev 121
|
||||
- ti,omap3630-gpu # Rev 125
|
||||
- const: img,powervr-sgx530
|
||||
- items:
|
||||
- enum:
|
||||
- ingenic,jz4780-gpu # Rev 130
|
||||
- ti,omap4430-gpu # Rev 120
|
||||
- const: img,powervr-sgx540
|
||||
- items:
|
||||
- enum:
|
||||
- allwinner,sun6i-a31-gpu # MP2 Rev 115
|
||||
- ti,omap4470-gpu # MP1 Rev 112
|
||||
- ti,omap5432-gpu # MP2 Rev 105
|
||||
- ti,am5728-gpu # MP2 Rev 116
|
||||
- ti,am6548-gpu # MP1 Rev 117
|
||||
- const: img,powervr-sgx544
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: core
|
||||
- const: mem
|
||||
- const: sys
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ti,am6548-gpu
|
||||
then:
|
||||
required:
|
||||
- power-domains
|
||||
else:
|
||||
properties:
|
||||
power-domains: false
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- allwinner,sun6i-a31-gpu
|
||||
- ingenic,jz4780-gpu
|
||||
then:
|
||||
required:
|
||||
- clocks
|
||||
- clock-names
|
||||
else:
|
||||
properties:
|
||||
clocks: false
|
||||
clock-names: false
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: allwinner,sun6i-a31-gpu
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
clock-names:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: ingenic,jz4780-gpu
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
gpu@7000000 {
|
||||
compatible = "ti,am6548-gpu", "img,powervr-sgx544";
|
||||
reg = <0x7000000 0x10000>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
gpu: gpu@1c40000 {
|
||||
compatible = "allwinner,sun6i-a31-gpu", "img,powervr-sgx544";
|
||||
reg = <0x01c40000 0x10000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&ccu 1>, <&ccu 2>;
|
||||
clock-names = "core", "mem";
|
||||
};
|
@ -10476,7 +10476,8 @@ M: Donald Robson <donald.robson@imgtec.com>
|
||||
M: Matt Coster <matt.coster@imgtec.com>
|
||||
S: Supported
|
||||
T: git git://anongit.freedesktop.org/drm/drm-misc
|
||||
F: Documentation/devicetree/bindings/gpu/img,powervr.yaml
|
||||
F: Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
|
||||
F: Documentation/devicetree/bindings/gpu/img,powervr-sgx.yaml
|
||||
F: Documentation/gpu/imagination/
|
||||
F: drivers/gpu/drm/imagination/
|
||||
F: include/uapi/drm/pvr_drm.h
|
||||
|
@ -640,10 +640,11 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x1000000>;
|
||||
|
||||
/*
|
||||
* Closed source PowerVR driver, no child device
|
||||
* binding or driver in mainline
|
||||
*/
|
||||
gpu@0 {
|
||||
compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
|
||||
reg = <0x0 0x10000>; /* 64kB */
|
||||
interrupts = <37>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -162,12 +162,13 @@
|
||||
clock-names = "fck", "ick";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x50000000 0x4000>;
|
||||
ranges = <0 0x50000000 0x10000>;
|
||||
|
||||
/*
|
||||
* Closed source PowerVR driver, no child device
|
||||
* binding or driver in mainline
|
||||
*/
|
||||
gpu@0 {
|
||||
compatible = "ti,omap3430-gpu", "img,powervr-sgx530";
|
||||
reg = <0x0 0x10000>; /* 64kB */
|
||||
interrupts = <21>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -719,6 +719,12 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x1000000>;
|
||||
|
||||
gpu@0 {
|
||||
compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
|
||||
reg = <0x0 0x10000>; /* 64kB */
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
@ -850,12 +850,19 @@
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x2000000>;
|
||||
|
||||
gpu@0 {
|
||||
compatible = "ti,am5728-gpu", "img,powervr-sgx544";
|
||||
reg = <0x0 0x10000>; /* 64kB */
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
crossbar_mpu: crossbar@4a002a48 {
|
||||
|
@ -164,12 +164,13 @@
|
||||
clock-names = "fck", "ick";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x50000000 0x4000>;
|
||||
ranges = <0 0x50000000 0x10000>;
|
||||
|
||||
/*
|
||||
* Closed source PowerVR driver, no child device
|
||||
* binding or driver in mainline
|
||||
*/
|
||||
gpu@0 {
|
||||
compatible = "ti,omap3430-gpu", "img,powervr-sgx530";
|
||||
reg = <0x0 0x10000>; /* 64kB */
|
||||
interrupts = <21>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -211,10 +211,11 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x50000000 0x2000000>;
|
||||
|
||||
/*
|
||||
* Closed source PowerVR driver, no child device
|
||||
* binding or driver in mainline
|
||||
*/
|
||||
gpu@0 {
|
||||
compatible = "ti,omap3630-gpu", "img,powervr-sgx530";
|
||||
reg = <0x0 0x2000000>; /* 32MB */
|
||||
interrupts = <21>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
@ -501,10 +501,11 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x2000000>;
|
||||
|
||||
/*
|
||||
* Closed source PowerVR driver, no child device
|
||||
* binding or driver in mainline
|
||||
*/
|
||||
gpu@0 {
|
||||
compatible = "ti,omap4430-gpu", "img,powervr-sgx540";
|
||||
reg = <0x0 0x2000000>; /* 32MB */
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
|
@ -453,10 +453,11 @@
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x2000000>;
|
||||
|
||||
/*
|
||||
* Closed source PowerVR driver, no child device
|
||||
* binding or driver in mainline
|
||||
*/
|
||||
gpu@0 {
|
||||
compatible = "ti,omap5432-gpu", "img,powervr-sgx544";
|
||||
reg = <0x0 0x2000000>; /* 32MB */
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@58000000 {
|
||||
|
@ -1050,6 +1050,13 @@
|
||||
};
|
||||
};
|
||||
|
||||
gpu: gpu@7000000 {
|
||||
compatible = "ti,am6548-gpu", "img,powervr-sgx544";
|
||||
reg = <0x0 0x7000000 0x0 0x10000>;
|
||||
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 65 TI_SCI_PD_EXCLUSIVE>;
|
||||
};
|
||||
|
||||
ehrpwm0: pwm@3000000 {
|
||||
compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
|
Loading…
Reference in New Issue
Block a user