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dt-bindings: net: convert rockchip-dwmac to json-schema
Convert Rockchip dwmac controller dt-bindings to YAML. Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: David Wu <david.wu@rock-chips.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ezequiel Garcia
David S. Miller
parent
517a882aa2
commit
b331b8ef86
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Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
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The device node has following properties.
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Required properties:
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- compatible: should be "rockchip,<name>-gamc"
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"rockchip,px30-gmac": found on PX30 SoCs
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"rockchip,rk3128-gmac": found on RK312x SoCs
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"rockchip,rk3228-gmac": found on RK322x SoCs
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"rockchip,rk3288-gmac": found on RK3288 SoCs
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"rockchip,rk3328-gmac": found on RK3328 SoCs
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"rockchip,rk3366-gmac": found on RK3366 SoCs
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"rockchip,rk3368-gmac": found on RK3368 SoCs
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"rockchip,rk3399-gmac": found on RK3399 SoCs
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"rockchip,rv1108-gmac": found on RV1108 SoCs
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- reg: addresses and length of the register sets for the device.
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- interrupts: Should contain the GMAC interrupts.
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- interrupt-names: Should contain the interrupt names "macirq".
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- rockchip,grf: phandle to the syscon grf used to control speed and mode.
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- clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
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<&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
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<&cru SCLK_MAC_RX>: clock gate for RX
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<&cru SCLK_MAC_TX>: clock gate for TX
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<&cru SCLK_MACREF>: clock gate for RMII referce clock
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<&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
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<&cru ACLK_GMAC>: AXI clock gate for GMAC
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<&cru PCLK_GMAC>: APB clock gate for GMAC
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- clock-names: One name for each entry in the clocks property.
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- phy-mode: See ethernet.txt file in the same directory.
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- pinctrl-names: Names corresponding to the numbered pinctrl states.
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- pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
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- clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
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is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
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PHY provides the reference clock(50MHz), "output" means GMAC provides the
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reference clock.
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- snps,reset-gpio gpio number for phy reset.
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- snps,reset-active-low boolean flag to indicate if phy reset is active low.
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- assigned-clocks: main clock, should be <&cru SCLK_MAC>;
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- assigned-clock-parents = parent of main clock.
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can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
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Optional properties:
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- tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
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- rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
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- phy-supply: phandle to a regulator if the PHY needs one
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Example:
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gmac: ethernet@ff290000 {
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compatible = "rockchip,rk3288-gmac";
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reg = <0xff290000 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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rockchip,grf = <&grf>;
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clocks = <&cru SCLK_MAC>,
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<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
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<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
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<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
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clock-names = "stmmaceth",
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"mac_clk_rx", "mac_clk_tx",
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"clk_mac_ref", "clk_mac_refout",
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"aclk_mac", "pclk_mac";
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>;
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clock_in_out = "input";
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snps,reset-gpio = <&gpio4 7 0>;
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snps,reset-active-low;
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assigned-clocks = <&cru SCLK_MAC>;
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assigned-clock-parents = <&ext_gmac>;
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tx_delay = <0x30>;
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rx_delay = <0x10>;
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};
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120
Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
Normal file
120
Documentation/devicetree/bindings/net/rockchip-dwmac.yaml
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/net/rockchip-dwmac.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Rockchip 10/100/1000 Ethernet driver(GMAC)
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maintainers:
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- David Wu <david.wu@rock-chips.com>
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# We need a select here so we don't match all nodes with 'snps,dwmac'
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select:
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properties:
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compatible:
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contains:
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enum:
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- rockchip,px30-gmac
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- rockchip,rk3128-gmac
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- rockchip,rk3228-gmac
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- rockchip,rk3288-gmac
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- rockchip,rk3328-gmac
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- rockchip,rk3366-gmac
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- rockchip,rk3368-gmac
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- rockchip,rk3399-gmac
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- rockchip,rv1108-gmac
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required:
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- compatible
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allOf:
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- $ref: "snps,dwmac.yaml#"
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properties:
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compatible:
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items:
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- enum:
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- rockchip,px30-gmac
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- rockchip,rk3128-gmac
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- rockchip,rk3228-gmac
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- rockchip,rk3288-gmac
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- rockchip,rk3328-gmac
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- rockchip,rk3366-gmac
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- rockchip,rk3368-gmac
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- rockchip,rk3399-gmac
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- rockchip,rv1108-gmac
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clocks:
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minItems: 5
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maxItems: 8
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clock-names:
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contains:
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enum:
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- stmmaceth
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- mac_clk_tx
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- mac_clk_rx
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- aclk_mac
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- pclk_mac
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- clk_mac_ref
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- clk_mac_refout
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- clk_mac_speed
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clock_in_out:
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description:
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For RGMII, it must be "input", means main clock(125MHz)
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is not sourced from SoC's PLL, but input from PHY.
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For RMII, "input" means PHY provides the reference clock(50MHz),
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"output" means GMAC provides the reference clock.
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$ref: /schemas/types.yaml#/definitions/string
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enum: [input, output]
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rockchip,grf:
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description: The phandle of the syscon node for the general register file.
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$ref: /schemas/types.yaml#/definitions/phandle
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tx_delay:
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description: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
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$ref: /schemas/types.yaml#/definitions/uint32
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rx_delay:
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description: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
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$ref: /schemas/types.yaml#/definitions/uint32
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phy-supply:
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description: PHY regulator
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required:
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- compatible
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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gmac: ethernet@ff290000 {
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compatible = "rockchip,rk3288-gmac";
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reg = <0xff290000 0x10000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&cru SCLK_MAC>,
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<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
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<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
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<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
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clock-names = "stmmaceth",
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"mac_clk_rx", "mac_clk_tx",
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"clk_mac_ref", "clk_mac_refout",
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"aclk_mac", "pclk_mac";
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assigned-clocks = <&cru SCLK_MAC>;
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assigned-clock-parents = <&ext_gmac>;
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rockchip,grf = <&grf>;
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phy-mode = "rgmii";
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clock_in_out = "input";
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tx_delay = <0x30>;
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rx_delay = <0x10>;
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};
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