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I2C: mediatek: Add driver for MediaTek MT8173 I2C controller
Add mediatek MT8173 I2C controller driver. Compare to I2C controller of earlier mediatek SoC, MT8173 fix write-then-read limitation, and also increase message size to 64kb. Signed-off-by: Xudong Chen <xudong.chen@mediatek.com> Signed-off-by: Liguo Zhang <liguo.zhang@mediatek.com> Signed-off-by: Eddie Huang <eddie.huang@mediatek.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
This commit is contained in:
Eddie Huang
Wolfram Sang
parent
ce38815d39
commit
b2ed11e224
@ -33,10 +33,13 @@
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#include <linux/sched.h>
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#include <linux/slab.h>
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#define I2C_RS_TRANSFER (1 << 4)
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#define I2C_HS_NACKERR (1 << 2)
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#define I2C_ACKERR (1 << 1)
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#define I2C_TRANSAC_COMP (1 << 0)
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#define I2C_TRANSAC_START (1 << 0)
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#define I2C_RS_MUL_CNFG (1 << 15)
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#define I2C_RS_MUL_TRIG (1 << 14)
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#define I2C_DCM_DISABLE 0x0000
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#define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
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#define I2C_IO_CONFIG_PUSH_PULL 0x0000
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@ -126,6 +129,7 @@ struct mtk_i2c_compatible {
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const struct i2c_adapter_quirks *quirks;
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unsigned char pmic_i2c: 1;
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unsigned char dcm: 1;
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unsigned char auto_restart: 1;
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};
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struct mtk_i2c {
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@ -159,21 +163,39 @@ static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
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.max_comb_2nd_msg_len = 31,
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};
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static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
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.max_num_msgs = 65535,
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.max_write_len = 65535,
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.max_read_len = 65535,
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.max_comb_1st_msg_len = 65535,
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.max_comb_2nd_msg_len = 65535,
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};
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static const struct mtk_i2c_compatible mt6577_compat = {
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.quirks = &mt6577_i2c_quirks,
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.pmic_i2c = 0,
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.dcm = 1,
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.auto_restart = 0,
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};
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static const struct mtk_i2c_compatible mt6589_compat = {
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.quirks = &mt6577_i2c_quirks,
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.pmic_i2c = 1,
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.dcm = 0,
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.auto_restart = 0,
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};
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static const struct mtk_i2c_compatible mt8173_compat = {
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.quirks = &mt8173_i2c_quirks,
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.pmic_i2c = 0,
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.dcm = 1,
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.auto_restart = 1,
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};
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static const struct of_device_id mtk_i2c_of_match[] = {
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{ .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
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{ .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
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{ .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
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{}
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};
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MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
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@ -332,21 +354,27 @@ static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk,
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return 0;
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}
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static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
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static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
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int num, int left_num)
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{
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u16 addr_reg;
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u16 start_reg;
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u16 control_reg;
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u16 restart_flag = 0;
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dma_addr_t rpaddr = 0;
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dma_addr_t wpaddr = 0;
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int ret;
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i2c->irq_stat = 0;
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if (i2c->dev_comp->auto_restart)
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restart_flag = I2C_RS_TRANSFER;
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reinit_completion(&i2c->msg_complete);
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control_reg = readw(i2c->base + OFFSET_CONTROL) &
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~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
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if (i2c->speed_hz > 400000)
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if ((i2c->speed_hz > 400000) || (left_num >= 1))
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control_reg |= I2C_CONTROL_RS;
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if (i2c->op == I2C_MASTER_WRRD)
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@ -367,13 +395,13 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
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writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
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/* Clear interrupt status */
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writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
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i2c->base + OFFSET_INTR_STAT);
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writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
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writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
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/* Enable interrupt */
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writew(I2C_HS_NACKERR | I2C_ACKERR | I2C_TRANSAC_COMP,
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i2c->base + OFFSET_INTR_MASK);
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writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
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/* Set transfer and transaction len */
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if (i2c->op == I2C_MASTER_WRRD) {
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@ -382,7 +410,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
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writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
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} else {
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writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
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writew(I2C_RD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
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writew(num, i2c->base + OFFSET_TRANSAC_LEN);
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}
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/* Prepare buffer data to start transfer */
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@ -426,13 +454,21 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs)
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}
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writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
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writew(I2C_TRANSAC_START, i2c->base + OFFSET_START);
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if (!i2c->dev_comp->auto_restart) {
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start_reg = I2C_TRANSAC_START;
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} else {
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start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
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if (left_num >= 1)
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start_reg |= I2C_RS_MUL_CNFG;
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}
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writew(start_reg, i2c->base + OFFSET_START);
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ret = wait_for_completion_timeout(&i2c->msg_complete,
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i2c->adap.timeout);
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/* Clear interrupt mask */
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writew(~(I2C_HS_NACKERR | I2C_ACKERR |
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writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
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I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
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if (i2c->op == I2C_MASTER_WR) {
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@ -476,28 +512,33 @@ static int mtk_i2c_transfer(struct i2c_adapter *adap,
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if (ret)
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return ret;
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if (!msgs->buf) {
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dev_dbg(i2c->dev, "data buffer is NULL.\n");
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ret = -EINVAL;
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goto err_exit;
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while (left_num--) {
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if (!msgs->buf) {
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dev_dbg(i2c->dev, "data buffer is NULL.\n");
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ret = -EINVAL;
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goto err_exit;
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}
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if (msgs->flags & I2C_M_RD)
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i2c->op = I2C_MASTER_RD;
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else
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i2c->op = I2C_MASTER_WR;
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if (!i2c->dev_comp->auto_restart) {
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if (num > 1) {
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/* combined two messages into one transaction */
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i2c->op = I2C_MASTER_WRRD;
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left_num--;
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}
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}
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/* always use DMA mode. */
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ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
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if (ret < 0)
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goto err_exit;
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msgs++;
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}
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if (msgs->flags & I2C_M_RD)
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i2c->op = I2C_MASTER_RD;
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else
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i2c->op = I2C_MASTER_WR;
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if (num > 1) {
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/* combined two messages into one transaction */
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i2c->op = I2C_MASTER_WRRD;
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left_num--;
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}
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/* always use DMA mode. */
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ret = mtk_i2c_do_transfer(i2c, msgs);
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if (ret < 0)
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goto err_exit;
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/* the return value is number of executed messages */
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ret = num;
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@ -509,9 +550,13 @@ err_exit:
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static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
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{
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struct mtk_i2c *i2c = dev_id;
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u16 restart_flag = 0;
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if (i2c->dev_comp->auto_restart)
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restart_flag = I2C_RS_TRANSFER;
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i2c->irq_stat = readw(i2c->base + OFFSET_INTR_STAT);
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writew(I2C_HS_NACKERR | I2C_ACKERR
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writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR
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| I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
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complete(&i2c->msg_complete);
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