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clk: samsung: exynos5433: Add clocks for CMU_MSCL domain
This patch adds the mux/divider/gate clocks for CMU_MSCL domain which generates the clocks for M2M (Memory to Memory) scaler, JPEG IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This commit is contained in:
Chanwoo Choi
Sylwester Nawrocki
parent
6c5d76d15a
commit
b274bbfd8b
@ -37,6 +37,8 @@ Required Properties:
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- "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
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which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
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L2 cache controller.
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- "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
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which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
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- reg: physical base address of the controller and length of memory mapped
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region.
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@ -118,6 +120,11 @@ Required Properties:
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- oscclk
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- sclk_bus_pll_atlas
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Input clocks for mscl clock controller:
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- oscclk
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- sclk_jpeg_mscl
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- aclk_mscl_400
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume.
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@ -320,6 +327,19 @@ Example 2: Examples of clock controller nodes are listed below.
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clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
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};
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cmu_mscl: clock-controller@105d0000 {
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compatible = "samsung,exynos5433-cmu-mscl";
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reg = <0x105d0000 0x0b10>;
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#clock-cells = <1>;
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clock-names = "oscclk",
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"sclk_jpeg_mscl",
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"aclk_mscl_400";
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clocks = <&xxti>,
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<&cmu_top CLK_SCLK_JPEG_MSCL>,
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<&cmu_top CLK_ACLK_MSCL_400>;
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};
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Example 3: UART controller node that consumes the clock generated by the clock
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controller.
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@ -419,6 +419,8 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
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DIV_TOP1, 0, 3),
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/* DIV_TOP2 */
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DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
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DIV_TOP2, 4, 3),
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DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
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DIV_TOP2, 0, 3),
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@ -446,6 +448,10 @@ static struct samsung_div_clock top_div_clks[] __initdata = {
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DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
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DIV_TOP4, 0, 3),
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/* DIV_TOP_MSCL */
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DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
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DIV_TOP_MSCL, 0, 4),
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/* DIV_TOP_FSYS0 */
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DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
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DIV_TOP_FSYS0, 16, 8),
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@ -542,6 +548,9 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
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GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
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ENABLE_ACLK_TOP, 21,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
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ENABLE_ACLK_TOP, 19,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
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ENABLE_ACLK_TOP, 18,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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@ -558,6 +567,10 @@ static struct samsung_gate_clock top_gate_clks[] __initdata = {
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ENABLE_ACLK_TOP, 0,
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CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
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/* ENABLE_SCLK_TOP_MSCL */
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GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
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ENABLE_SCLK_TOP_MSCL, 0, 0, 0),
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/* ENABLE_SCLK_TOP_FSYS */
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GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
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ENABLE_SCLK_TOP_FSYS, 7, 0, 0),
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@ -3805,3 +3818,175 @@ static void __init exynos5433_cmu_atlas_init(struct device_node *np)
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}
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CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
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exynos5433_cmu_atlas_init);
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/*
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* Register offset definitions for CMU_MSCL
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*/
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#define MUX_SEL_MSCL0 0x0200
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#define MUX_SEL_MSCL1 0x0204
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#define MUX_ENABLE_MSCL0 0x0300
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#define MUX_ENABLE_MSCL1 0x0304
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#define MUX_STAT_MSCL0 0x0400
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#define MUX_STAT_MSCL1 0x0404
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#define DIV_MSCL 0x0600
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#define DIV_STAT_MSCL 0x0700
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#define ENABLE_ACLK_MSCL 0x0800
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#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
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#define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
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#define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
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#define ENABLE_PCLK_MSCL 0x0900
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#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
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#define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
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#define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x000c
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#define ENABLE_SCLK_MSCL 0x0a00
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#define ENABLE_IP_MSCL0 0x0b00
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#define ENABLE_IP_MSCL1 0x0b04
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#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
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#define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
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#define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
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static unsigned long mscl_clk_regs[] __initdata = {
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MUX_SEL_MSCL0,
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MUX_SEL_MSCL1,
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MUX_ENABLE_MSCL0,
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MUX_ENABLE_MSCL1,
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MUX_STAT_MSCL0,
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MUX_STAT_MSCL1,
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DIV_MSCL,
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DIV_STAT_MSCL,
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ENABLE_ACLK_MSCL,
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ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
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ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
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ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
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ENABLE_PCLK_MSCL,
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ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
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ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
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ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
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ENABLE_SCLK_MSCL,
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ENABLE_IP_MSCL0,
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ENABLE_IP_MSCL1,
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ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
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ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
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ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
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};
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/* list of all parent clock list */
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PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
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PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
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PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
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"mout_aclk_mscl_400_user", };
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static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
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/* MUX_SEL_MSCL0 */
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MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
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mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
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MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
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mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
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/* MUX_SEL_MSCL1 */
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MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
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MUX_SEL_MSCL1, 0, 1),
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};
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static struct samsung_div_clock mscl_div_clks[] __initdata = {
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/* DIV_MSCL */
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DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
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DIV_MSCL, 0, 3),
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};
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static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
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/* ENABLE_ACLK_MSCL */
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GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
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ENABLE_ACLK_MSCL, 9, 0, 0),
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GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
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"mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
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GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
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"mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
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GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
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ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
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ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
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ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
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ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
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ENABLE_ACLK_MSCL, 2, 0, 0),
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GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
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ENABLE_ACLK_MSCL, 1, 0, 0),
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GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
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ENABLE_ACLK_MSCL, 0, 0, 0),
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/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
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GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
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"mout_aclk_mscl_400_user",
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ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
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GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
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"mout_aclk_mscl_400_user",
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ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
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GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
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ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_MSCL */
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GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
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ENABLE_PCLK_MSCL, 7, 0, 0),
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GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
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ENABLE_PCLK_MSCL, 6, 0, 0),
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GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
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ENABLE_PCLK_MSCL, 5, 0, 0),
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GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
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ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
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ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
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GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
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ENABLE_PCLK_MSCL, 2, 0, 0),
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GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
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ENABLE_PCLK_MSCL, 1, 0, 0),
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GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
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ENABLE_PCLK_MSCL, 0, 0, 0),
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/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
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GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
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ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
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GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
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ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
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GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
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ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
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0, CLK_IGNORE_UNUSED, 0),
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/* ENABLE_SCLK_MSCL */
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GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
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CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_cmu_info mscl_cmu_info __initdata = {
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.mux_clks = mscl_mux_clks,
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.nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
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.div_clks = mscl_div_clks,
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.nr_div_clks = ARRAY_SIZE(mscl_div_clks),
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.gate_clks = mscl_gate_clks,
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.nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
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.nr_clk_ids = MSCL_NR_CLK,
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.clk_regs = mscl_clk_regs,
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.nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
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};
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static void __init exynos5433_cmu_mscl_init(struct device_node *np)
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{
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samsung_cmu_register_one(np, &mscl_cmu_info);
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}
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CLK_OF_DECLARE(exynos5433_cmu_mscl, "samsung,exynos5433-cmu-mscl",
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exynos5433_cmu_mscl_init);
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@ -114,6 +114,8 @@
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#define CLK_DIV_SCLK_USBHOST30 141
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#define CLK_DIV_SCLK_UFSUNIPRO 142
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#define CLK_DIV_SCLK_USBDRD30 143
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#define CLK_DIV_SCLK_JPEG 144
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#define CLK_DIV_ACLK_MSCL_400 145
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#define CLK_ACLK_PERIC_66 200
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#define CLK_ACLK_PERIS_66 201
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@ -149,8 +151,10 @@
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#define CLK_SCLK_USBDRD30_FSYS 231
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#define CLK_ACLK_GSCL_111 232
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#define CLK_ACLK_GSCL_333 233
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#define CLK_SCLK_JPEG_MSCL 234
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#define CLK_ACLK_MSCL_400 235
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#define TOP_NR_CLK 234
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#define TOP_NR_CLK 236
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/* CMU_CPIF */
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#define CLK_FOUT_MPHY_PLL 1
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@ -937,4 +941,39 @@
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#define ATLAS_NR_CLK 40
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/* CMU_MSCL */
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#define CLK_MOUT_SCLK_JPEG_USER 1
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#define CLK_MOUT_ACLK_MSCL_400_USER 2
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#define CLK_MOUT_SCLK_JPEG 3
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#define CLK_DIV_PCLK_MSCL 4
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#define CLK_ACLK_BTS_JPEG 5
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#define CLK_ACLK_BTS_M2MSCALER1 6
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#define CLK_ACLK_BTS_M2MSCALER0 7
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#define CLK_ACLK_AHB2APB_MSCL0P 8
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#define CLK_ACLK_XIU_MSCLX 9
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#define CLK_ACLK_MSCLNP_100 10
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#define CLK_ACLK_MSCLND_400 11
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#define CLK_ACLK_JPEG 12
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#define CLK_ACLK_M2MSCALER1 13
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#define CLK_ACLK_M2MSCALER0 14
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#define CLK_ACLK_SMMU_M2MSCALER0 15
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#define CLK_ACLK_SMMU_M2MSCALER1 16
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#define CLK_ACLK_SMMU_JPEG 17
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#define CLK_PCLK_BTS_JPEG 18
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#define CLK_PCLK_BTS_M2MSCALER1 19
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#define CLK_PCLK_BTS_M2MSCALER0 20
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#define CLK_PCLK_PMU_MSCL 21
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#define CLK_PCLK_SYSREG_MSCL 22
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#define CLK_PCLK_JPEG 23
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#define CLK_PCLK_M2MSCALER1 24
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#define CLK_PCLK_M2MSCALER0 25
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#define CLK_PCLK_SMMU_M2MSCALER0 26
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#define CLK_PCLK_SMMU_M2MSCALER1 27
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#define CLK_PCLK_SMMU_JPEG 28
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#define CLK_SCLK_JPEG 29
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#define MSCL_NR_CLK 30
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
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