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WAN: Convert PC300 driver to use normal u8/u16/u32 types
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
This commit is contained in:
Krzysztof Hałasa
parent
c36936ce4b
commit
b22267d388
@ -103,10 +103,6 @@
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#include "hd64572.h"
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#include "pc300-falc-lh.h"
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typedef __u32 uclong; /* 32 bits, unsigned */
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typedef __u16 ucshort; /* 16 bits, unsigned */
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typedef __u8 ucchar; /* 8 bits, unsigned */
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#define PC300_PROTO_MLPPP 1
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#define PC300_MAXCHAN 2 /* Number of channels per card */
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@ -147,9 +143,9 @@ typedef __u8 ucchar; /* 8 bits, unsigned */
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* Memory access functions/macros *
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* (required to support Alpha systems) *
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***************************************/
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#define cpc_writeb(port,val) {writeb((ucchar)(val),(port)); mb();}
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#define cpc_writeb(port,val) {writeb((u8)(val),(port)); mb();}
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#define cpc_writew(port,val) {writew((ushort)(val),(port)); mb();}
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#define cpc_writel(port,val) {writel((uclong)(val),(port)); mb();}
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#define cpc_writel(port,val) {writel((u32)(val),(port)); mb();}
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#define cpc_readb(port) readb(port)
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#define cpc_readw(port) readw(port)
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@ -163,15 +159,15 @@ typedef __u8 ucchar; /* 8 bits, unsigned */
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* (memory mapped).
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*/
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struct RUNTIME_9050 {
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uclong loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
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uclong loc_rom_range; /* 10h : Local ROM Range */
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uclong loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
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uclong loc_rom_base; /* 24h : Local ROM Base */
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uclong loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
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uclong rom_bus_descr; /* 38h : ROM Bus Descriptor */
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uclong cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
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uclong intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
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uclong init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
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u32 loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
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u32 loc_rom_range; /* 10h : Local ROM Range */
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u32 loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
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u32 loc_rom_base; /* 24h : Local ROM Base */
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u32 loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
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u32 rom_bus_descr; /* 38h : ROM Bus Descriptor */
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u32 cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
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u32 intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
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u32 init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
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};
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#define PLX_9050_LINT1_ENABLE 0x01
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@ -215,66 +211,66 @@ struct RUNTIME_9050 {
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#define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */
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typedef struct falc {
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ucchar sync; /* If true FALC is synchronized */
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ucchar active; /* if TRUE then already active */
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ucchar loop_active; /* if TRUE a line loopback UP was received */
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ucchar loop_gen; /* if TRUE a line loopback UP was issued */
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u8 sync; /* If true FALC is synchronized */
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u8 active; /* if TRUE then already active */
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u8 loop_active; /* if TRUE a line loopback UP was received */
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u8 loop_gen; /* if TRUE a line loopback UP was issued */
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ucchar num_channels;
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ucchar offset; /* 1 for T1, 0 for E1 */
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ucchar full_bandwidth;
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u8 num_channels;
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u8 offset; /* 1 for T1, 0 for E1 */
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u8 full_bandwidth;
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ucchar xmb_cause;
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ucchar multiframe_mode;
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u8 xmb_cause;
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u8 multiframe_mode;
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/* Statistics */
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ucshort pden; /* Pulse Density violation count */
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ucshort los; /* Loss of Signal count */
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ucshort losr; /* Loss of Signal recovery count */
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ucshort lfa; /* Loss of frame alignment count */
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ucshort farec; /* Frame Alignment Recovery count */
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ucshort lmfa; /* Loss of multiframe alignment count */
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ucshort ais; /* Remote Alarm indication Signal count */
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ucshort sec; /* One-second timer */
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ucshort es; /* Errored second */
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ucshort rai; /* remote alarm received */
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ucshort bec;
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ucshort fec;
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ucshort cvc;
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ucshort cec;
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ucshort ebc;
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u16 pden; /* Pulse Density violation count */
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u16 los; /* Loss of Signal count */
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u16 losr; /* Loss of Signal recovery count */
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u16 lfa; /* Loss of frame alignment count */
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u16 farec; /* Frame Alignment Recovery count */
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u16 lmfa; /* Loss of multiframe alignment count */
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u16 ais; /* Remote Alarm indication Signal count */
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u16 sec; /* One-second timer */
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u16 es; /* Errored second */
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u16 rai; /* remote alarm received */
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u16 bec;
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u16 fec;
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u16 cvc;
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u16 cec;
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u16 ebc;
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/* Status */
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ucchar red_alarm;
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ucchar blue_alarm;
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ucchar loss_fa;
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ucchar yellow_alarm;
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ucchar loss_mfa;
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ucchar prbs;
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u8 red_alarm;
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u8 blue_alarm;
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u8 loss_fa;
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u8 yellow_alarm;
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u8 loss_mfa;
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u8 prbs;
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} falc_t;
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typedef struct falc_status {
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ucchar sync; /* If true FALC is synchronized */
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ucchar red_alarm;
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ucchar blue_alarm;
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ucchar loss_fa;
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ucchar yellow_alarm;
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ucchar loss_mfa;
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ucchar prbs;
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u8 sync; /* If true FALC is synchronized */
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u8 red_alarm;
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u8 blue_alarm;
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u8 loss_fa;
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u8 yellow_alarm;
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u8 loss_mfa;
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u8 prbs;
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} falc_status_t;
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typedef struct rsv_x21_status {
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ucchar dcd;
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ucchar dsr;
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ucchar cts;
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ucchar rts;
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ucchar dtr;
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u8 dcd;
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u8 dsr;
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u8 cts;
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u8 rts;
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u8 dtr;
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} rsv_x21_status_t;
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typedef struct pc300stats {
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int hw_type;
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uclong line_on;
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uclong line_off;
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u32 line_on;
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u32 line_off;
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struct net_device_stats gen_stats;
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falc_t te_stats;
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} pc300stats_t;
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@ -292,14 +288,14 @@ typedef struct pc300loopback {
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typedef struct pc300patterntst {
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char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */
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ucshort num_errors;
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u16 num_errors;
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} pc300patterntst_t;
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typedef struct pc300dev {
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struct pc300ch *chan;
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ucchar trace_on;
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uclong line_on; /* DCD(X.21, RSV) / sync(TE) change counters */
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uclong line_off;
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u8 trace_on;
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u32 line_on; /* DCD(X.21, RSV) / sync(TE) change counters */
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u32 line_off;
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char name[16];
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struct net_device *dev;
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#ifdef CONFIG_PC300_MLPPP
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@ -312,42 +308,42 @@ typedef struct pc300hw {
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int bus; /* Bus (PCI, PMC, etc.) */
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int nchan; /* number of channels */
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int irq; /* interrupt request level */
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uclong clock; /* Board clock */
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ucchar cpld_id; /* CPLD ID (TE only) */
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ucshort cpld_reg1; /* CPLD reg 1 (TE only) */
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ucshort cpld_reg2; /* CPLD reg 2 (TE only) */
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ucshort gpioc_reg; /* PLX GPIOC reg */
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ucshort intctl_reg; /* PLX Int Ctrl/Status reg */
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uclong iophys; /* PLX registers I/O base */
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uclong iosize; /* PLX registers I/O size */
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uclong plxphys; /* PLX registers MMIO base (physical) */
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u32 clock; /* Board clock */
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u8 cpld_id; /* CPLD ID (TE only) */
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u16 cpld_reg1; /* CPLD reg 1 (TE only) */
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u16 cpld_reg2; /* CPLD reg 2 (TE only) */
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u16 gpioc_reg; /* PLX GPIOC reg */
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u16 intctl_reg; /* PLX Int Ctrl/Status reg */
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u32 iophys; /* PLX registers I/O base */
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u32 iosize; /* PLX registers I/O size */
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u32 plxphys; /* PLX registers MMIO base (physical) */
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void __iomem * plxbase; /* PLX registers MMIO base (virtual) */
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uclong plxsize; /* PLX registers MMIO size */
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uclong scaphys; /* SCA registers MMIO base (physical) */
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u32 plxsize; /* PLX registers MMIO size */
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u32 scaphys; /* SCA registers MMIO base (physical) */
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void __iomem * scabase; /* SCA registers MMIO base (virtual) */
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uclong scasize; /* SCA registers MMIO size */
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uclong ramphys; /* On-board RAM MMIO base (physical) */
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u32 scasize; /* SCA registers MMIO size */
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u32 ramphys; /* On-board RAM MMIO base (physical) */
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void __iomem * rambase; /* On-board RAM MMIO base (virtual) */
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uclong alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */
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uclong ramsize; /* On-board RAM MMIO size */
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uclong falcphys; /* FALC registers MMIO base (physical) */
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u32 alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */
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u32 ramsize; /* On-board RAM MMIO size */
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u32 falcphys; /* FALC registers MMIO base (physical) */
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void __iomem * falcbase;/* FALC registers MMIO base (virtual) */
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uclong falcsize; /* FALC registers MMIO size */
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u32 falcsize; /* FALC registers MMIO size */
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} pc300hw_t;
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typedef struct pc300chconf {
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sync_serial_settings phys_settings; /* Clock type/rate (in bps),
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loopback mode */
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raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */
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uclong media; /* HW media (RS232, V.35, etc.) */
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uclong proto; /* Protocol (PPP, X.25, etc.) */
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u32 media; /* HW media (RS232, V.35, etc.) */
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u32 proto; /* Protocol (PPP, X.25, etc.) */
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/* TE-specific parameters */
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ucchar lcode; /* Line Code (AMI, B8ZS, etc.) */
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ucchar fr_mode; /* Frame Mode (ESF, D4, etc.) */
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ucchar lbo; /* Line Build Out */
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ucchar rx_sens; /* Rx Sensitivity (long- or short-haul) */
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uclong tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */
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u8 lcode; /* Line Code (AMI, B8ZS, etc.) */
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u8 fr_mode; /* Frame Mode (ESF, D4, etc.) */
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u8 lbo; /* Line Build Out */
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u8 rx_sens; /* Rx Sensitivity (long- or short-haul) */
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u32 tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */
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} pc300chconf_t;
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typedef struct pc300ch {
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@ -355,11 +351,11 @@ typedef struct pc300ch {
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int channel;
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pc300dev_t d;
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pc300chconf_t conf;
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ucchar tx_first_bd; /* First TX DMA block descr. w/ data */
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ucchar tx_next_bd; /* Next free TX DMA block descriptor */
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ucchar rx_first_bd; /* First free RX DMA block descriptor */
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ucchar rx_last_bd; /* Last free RX DMA block descriptor */
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ucchar nfree_tx_bd; /* Number of free TX DMA block descriptors */
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u8 tx_first_bd; /* First TX DMA block descr. w/ data */
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u8 tx_next_bd; /* Next free TX DMA block descriptor */
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u8 rx_first_bd; /* First free RX DMA block descriptor */
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u8 rx_last_bd; /* Last free RX DMA block descriptor */
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u8 nfree_tx_bd; /* Number of free TX DMA block descriptors */
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falc_t falc; /* FALC structure (TE only) */
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} pc300ch_t;
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@ -283,8 +283,8 @@ static void rx_dma_buf_init(pc300_t *, int);
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static void tx_dma_buf_check(pc300_t *, int);
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static void rx_dma_buf_check(pc300_t *, int);
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static irqreturn_t cpc_intr(int, void *);
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static int clock_rate_calc(uclong, uclong, int *);
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static uclong detect_ram(pc300_t *);
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static int clock_rate_calc(u32, u32, int *);
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static u32 detect_ram(pc300_t *);
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static void plx_init(pc300_t *);
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static void cpc_trace(struct net_device *, struct sk_buff *, char);
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static int cpc_attach(struct net_device *, unsigned short, unsigned short);
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@ -309,10 +309,10 @@ static void tx_dma_buf_pt_init(pc300_t * card, int ch)
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+ DMA_TX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
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for (i = 0; i < N_DMA_TX_BUF; i++, ptdescr++) {
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cpc_writel(&ptdescr->next, (uclong) (DMA_TX_BD_BASE +
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cpc_writel(&ptdescr->next, (u32)(DMA_TX_BD_BASE +
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(ch_factor + ((i + 1) & (N_DMA_TX_BUF - 1))) * sizeof(pcsca_bd_t)));
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cpc_writel(&ptdescr->ptbuf,
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(uclong) (DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
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(u32)(DMA_TX_BASE + (ch_factor + i) * BD_DEF_LEN));
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}
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}
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@ -339,10 +339,10 @@ static void rx_dma_buf_pt_init(pc300_t * card, int ch)
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+ DMA_RX_BD_BASE + ch_factor * sizeof(pcsca_bd_t));
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for (i = 0; i < N_DMA_RX_BUF; i++, ptdescr++) {
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cpc_writel(&ptdescr->next, (uclong) (DMA_RX_BD_BASE +
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cpc_writel(&ptdescr->next, (u32)(DMA_RX_BD_BASE +
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(ch_factor + ((i + 1) & (N_DMA_RX_BUF - 1))) * sizeof(pcsca_bd_t)));
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cpc_writel(&ptdescr->ptbuf,
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(uclong) (DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
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(u32)(DMA_RX_BASE + (ch_factor + i) * BD_DEF_LEN));
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}
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}
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@ -365,8 +365,8 @@ static void tx_dma_buf_check(pc300_t * card, int ch)
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{
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volatile pcsca_bd_t __iomem *ptdescr;
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int i;
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ucshort first_bd = card->chan[ch].tx_first_bd;
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ucshort next_bd = card->chan[ch].tx_next_bd;
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u16 first_bd = card->chan[ch].tx_first_bd;
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u16 next_bd = card->chan[ch].tx_next_bd;
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printk("#CH%d: f_bd = %d(0x%08zx), n_bd = %d(0x%08zx)\n", ch,
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first_bd, TX_BD_ADDR(ch, first_bd),
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@ -390,9 +390,9 @@ static void tx1_dma_buf_check(pc300_t * card, int ch)
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{
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volatile pcsca_bd_t __iomem *ptdescr;
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int i;
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ucshort first_bd = card->chan[ch].tx_first_bd;
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ucshort next_bd = card->chan[ch].tx_next_bd;
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uclong scabase = card->hw.scabase;
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u16 first_bd = card->chan[ch].tx_first_bd;
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u16 next_bd = card->chan[ch].tx_next_bd;
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u32 scabase = card->hw.scabase;
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printk ("\nnfree_tx_bd = %d \n", card->chan[ch].nfree_tx_bd);
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printk("#CH%d: f_bd = %d(0x%08x), n_bd = %d(0x%08x)\n", ch,
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@ -416,8 +416,8 @@ static void rx_dma_buf_check(pc300_t * card, int ch)
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{
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volatile pcsca_bd_t __iomem *ptdescr;
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int i;
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ucshort first_bd = card->chan[ch].rx_first_bd;
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ucshort last_bd = card->chan[ch].rx_last_bd;
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u16 first_bd = card->chan[ch].rx_first_bd;
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u16 last_bd = card->chan[ch].rx_last_bd;
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int ch_factor;
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ch_factor = ch * N_DMA_RX_BUF;
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@ -438,9 +438,9 @@ static void rx_dma_buf_check(pc300_t * card, int ch)
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static int dma_get_rx_frame_size(pc300_t * card, int ch)
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{
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volatile pcsca_bd_t __iomem *ptdescr;
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ucshort first_bd = card->chan[ch].rx_first_bd;
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u16 first_bd = card->chan[ch].rx_first_bd;
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int rcvd = 0;
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volatile ucchar status;
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volatile u8 status;
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ptdescr = (card->hw.rambase + RX_BD_ADDR(ch, first_bd));
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while ((status = cpc_readb(&ptdescr->status)) & DST_OSB) {
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@ -460,12 +460,12 @@ static int dma_get_rx_frame_size(pc300_t * card, int ch)
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* dma_buf_write: writes a frame to the Tx DMA buffers
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* NOTE: this function writes one frame at a time.
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*/
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static int dma_buf_write(pc300_t * card, int ch, ucchar * ptdata, int len)
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static int dma_buf_write(pc300_t *card, int ch, u8 *ptdata, int len)
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{
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int i, nchar;
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volatile pcsca_bd_t __iomem *ptdescr;
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int tosend = len;
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ucchar nbuf = ((len - 1) / BD_DEF_LEN) + 1;
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u8 nbuf = ((len - 1) / BD_DEF_LEN) + 1;
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if (nbuf >= card->chan[ch].nfree_tx_bd) {
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return -ENOMEM;
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@ -507,7 +507,7 @@ static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
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pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
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volatile pcsca_bd_t __iomem *ptdescr;
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int rcvd = 0;
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volatile ucchar status;
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volatile u8 status;
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ptdescr = (card->hw.rambase +
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RX_BD_ADDR(ch, chan->rx_first_bd));
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@ -561,8 +561,8 @@ static int dma_buf_read(pc300_t * card, int ch, struct sk_buff *skb)
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static void tx_dma_stop(pc300_t * card, int ch)
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{
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void __iomem *scabase = card->hw.scabase;
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||||
ucchar drr_ena_bit = 1 << (5 + 2 * ch);
|
||||
ucchar drr_rst_bit = 1 << (1 + 2 * ch);
|
||||
u8 drr_ena_bit = 1 << (5 + 2 * ch);
|
||||
u8 drr_rst_bit = 1 << (1 + 2 * ch);
|
||||
|
||||
/* Disable DMA */
|
||||
cpc_writeb(scabase + DRR, drr_ena_bit);
|
||||
@ -572,8 +572,8 @@ static void tx_dma_stop(pc300_t * card, int ch)
|
||||
static void rx_dma_stop(pc300_t * card, int ch)
|
||||
{
|
||||
void __iomem *scabase = card->hw.scabase;
|
||||
ucchar drr_ena_bit = 1 << (4 + 2 * ch);
|
||||
ucchar drr_rst_bit = 1 << (2 * ch);
|
||||
u8 drr_ena_bit = 1 << (4 + 2 * ch);
|
||||
u8 drr_rst_bit = 1 << (2 * ch);
|
||||
|
||||
/* Disable DMA */
|
||||
cpc_writeb(scabase + DRR, drr_ena_bit);
|
||||
@ -605,7 +605,7 @@ static void rx_dma_start(pc300_t * card, int ch)
|
||||
/*************************/
|
||||
/*** FALC Routines ***/
|
||||
/*************************/
|
||||
static void falc_issue_cmd(pc300_t * card, int ch, ucchar cmd)
|
||||
static void falc_issue_cmd(pc300_t *card, int ch, u8 cmd)
|
||||
{
|
||||
void __iomem *falcbase = card->hw.falcbase;
|
||||
unsigned long i = 0;
|
||||
@ -673,7 +673,7 @@ static void falc_intr_enable(pc300_t * card, int ch)
|
||||
static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
|
||||
{
|
||||
void __iomem *falcbase = card->hw.falcbase;
|
||||
ucchar tshf = card->chan[ch].falc.offset;
|
||||
u8 tshf = card->chan[ch].falc.offset;
|
||||
|
||||
cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
|
||||
cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) &
|
||||
@ -689,7 +689,7 @@ static void falc_open_timeslot(pc300_t * card, int ch, int timeslot)
|
||||
static void falc_close_timeslot(pc300_t * card, int ch, int timeslot)
|
||||
{
|
||||
void __iomem *falcbase = card->hw.falcbase;
|
||||
ucchar tshf = card->chan[ch].falc.offset;
|
||||
u8 tshf = card->chan[ch].falc.offset;
|
||||
|
||||
cpc_writeb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch),
|
||||
cpc_readb(falcbase + F_REG((ICB1 + (timeslot - tshf) / 8), ch)) |
|
||||
@ -810,7 +810,7 @@ static void falc_init_t1(pc300_t * card, int ch)
|
||||
pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
|
||||
falc_t *pfalc = (falc_t *) & chan->falc;
|
||||
void __iomem *falcbase = card->hw.falcbase;
|
||||
ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
|
||||
u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
|
||||
|
||||
/* Switch to T1 mode (PCM 24) */
|
||||
cpc_writeb(falcbase + F_REG(FMR1, ch), FMR1_PMOD);
|
||||
@ -979,7 +979,7 @@ static void falc_init_e1(pc300_t * card, int ch)
|
||||
pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
|
||||
falc_t *pfalc = (falc_t *) & chan->falc;
|
||||
void __iomem *falcbase = card->hw.falcbase;
|
||||
ucchar dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
|
||||
u8 dja = (ch ? (LIM2_DJA2 | LIM2_DJA1) : 0);
|
||||
|
||||
/* Switch to E1 mode (PCM 30) */
|
||||
cpc_writeb(falcbase + F_REG(FMR1, ch),
|
||||
@ -1185,7 +1185,7 @@ static void te_config(pc300_t * card, int ch)
|
||||
pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
|
||||
falc_t *pfalc = (falc_t *) & chan->falc;
|
||||
void __iomem *falcbase = card->hw.falcbase;
|
||||
ucchar dummy;
|
||||
u8 dummy;
|
||||
unsigned long flags;
|
||||
|
||||
memset(pfalc, 0, sizeof(falc_t));
|
||||
@ -1401,7 +1401,7 @@ static void falc_update_stats(pc300_t * card, int ch)
|
||||
pc300chconf_t *conf = (pc300chconf_t *) & chan->conf;
|
||||
falc_t *pfalc = (falc_t *) & chan->falc;
|
||||
void __iomem *falcbase = card->hw.falcbase;
|
||||
ucshort counter;
|
||||
u16 counter;
|
||||
|
||||
counter = cpc_readb(falcbase + F_REG(FECL, ch));
|
||||
counter |= cpc_readb(falcbase + F_REG(FECH, ch)) << 8;
|
||||
@ -1727,7 +1727,7 @@ static void falc_pattern_test(pc300_t * card, int ch, unsigned int activate)
|
||||
* Description: This routine returns the bit error counter value
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
static ucshort falc_pattern_test_error(pc300_t * card, int ch)
|
||||
static u16 falc_pattern_test_error(pc300_t * card, int ch)
|
||||
{
|
||||
pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
|
||||
falc_t *pfalc = (falc_t *) & chan->falc;
|
||||
@ -1774,7 +1774,7 @@ static void cpc_tx_timeout(struct net_device *dev)
|
||||
pc300_t *card = (pc300_t *) chan->card;
|
||||
int ch = chan->channel;
|
||||
unsigned long flags;
|
||||
ucchar ilar;
|
||||
u8 ilar;
|
||||
|
||||
dev->stats.tx_errors++;
|
||||
dev->stats.tx_aborted_errors++;
|
||||
@ -1830,7 +1830,7 @@ static int cpc_queue_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||
}
|
||||
|
||||
/* Write buffer to DMA buffers */
|
||||
if (dma_buf_write(card, ch, (ucchar *) skb->data, skb->len) != 0) {
|
||||
if (dma_buf_write(card, ch, (u8 *)skb->data, skb->len) != 0) {
|
||||
// printk("%s: write error. Dropping TX packet.\n", dev->name);
|
||||
netif_stop_queue(dev);
|
||||
dev_kfree_skb(skb);
|
||||
@ -1995,7 +1995,7 @@ static void sca_tx_intr(pc300dev_t *dev)
|
||||
static void sca_intr(pc300_t * card)
|
||||
{
|
||||
void __iomem *scabase = card->hw.scabase;
|
||||
volatile uclong status;
|
||||
volatile u32 status;
|
||||
int ch;
|
||||
int intr_count = 0;
|
||||
unsigned char dsr_rx;
|
||||
@ -2010,7 +2010,7 @@ static void sca_intr(pc300_t * card)
|
||||
|
||||
/**** Reception ****/
|
||||
if (status & IR0_DRX((IR0_DMIA | IR0_DMIB), ch)) {
|
||||
ucchar drx_stat = cpc_readb(scabase + DSR_RX(ch));
|
||||
u8 drx_stat = cpc_readb(scabase + DSR_RX(ch));
|
||||
|
||||
/* Clear RX interrupts */
|
||||
cpc_writeb(scabase + DSR_RX(ch), drx_stat | DSR_DWE);
|
||||
@ -2084,7 +2084,7 @@ static void sca_intr(pc300_t * card)
|
||||
|
||||
/**** Transmission ****/
|
||||
if (status & IR0_DTX((IR0_EFT | IR0_DMIA | IR0_DMIB), ch)) {
|
||||
ucchar dtx_stat = cpc_readb(scabase + DSR_TX(ch));
|
||||
u8 dtx_stat = cpc_readb(scabase + DSR_TX(ch));
|
||||
|
||||
/* Clear TX interrupts */
|
||||
cpc_writeb(scabase + DSR_TX(ch), dtx_stat | DSR_DWE);
|
||||
@ -2128,7 +2128,7 @@ static void sca_intr(pc300_t * card)
|
||||
|
||||
/**** MSCI ****/
|
||||
if (status & IR0_M(IR0_RXINTA, ch)) {
|
||||
ucchar st1 = cpc_readb(scabase + M_REG(ST1, ch));
|
||||
u8 st1 = cpc_readb(scabase + M_REG(ST1, ch));
|
||||
|
||||
/* Clear MSCI interrupts */
|
||||
cpc_writeb(scabase + M_REG(ST1, ch), st1);
|
||||
@ -2170,7 +2170,7 @@ static void sca_intr(pc300_t * card)
|
||||
}
|
||||
}
|
||||
|
||||
static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1)
|
||||
static void falc_t1_loop_detection(pc300_t *card, int ch, u8 frs1)
|
||||
{
|
||||
pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
|
||||
falc_t *pfalc = (falc_t *) & chan->falc;
|
||||
@ -2195,7 +2195,7 @@ static void falc_t1_loop_detection(pc300_t * card, int ch, ucchar frs1)
|
||||
}
|
||||
}
|
||||
|
||||
static void falc_e1_loop_detection(pc300_t * card, int ch, ucchar rsp)
|
||||
static void falc_e1_loop_detection(pc300_t *card, int ch, u8 rsp)
|
||||
{
|
||||
pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
|
||||
falc_t *pfalc = (falc_t *) & chan->falc;
|
||||
@ -2225,8 +2225,8 @@ static void falc_t1_intr(pc300_t * card, int ch)
|
||||
pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
|
||||
falc_t *pfalc = (falc_t *) & chan->falc;
|
||||
void __iomem *falcbase = card->hw.falcbase;
|
||||
ucchar isr0, isr3, gis;
|
||||
ucchar dummy;
|
||||
u8 isr0, isr3, gis;
|
||||
u8 dummy;
|
||||
|
||||
while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
|
||||
if (gis & GIS_ISR0) {
|
||||
@ -2272,8 +2272,8 @@ static void falc_e1_intr(pc300_t * card, int ch)
|
||||
pc300ch_t *chan = (pc300ch_t *) & card->chan[ch];
|
||||
falc_t *pfalc = (falc_t *) & chan->falc;
|
||||
void __iomem *falcbase = card->hw.falcbase;
|
||||
ucchar isr1, isr2, isr3, gis, rsp;
|
||||
ucchar dummy;
|
||||
u8 isr1, isr2, isr3, gis, rsp;
|
||||
u8 dummy;
|
||||
|
||||
while ((gis = cpc_readb(falcbase + F_REG(GIS, ch))) != 0) {
|
||||
rsp = cpc_readb(falcbase + F_REG(RSP, ch));
|
||||
@ -2355,7 +2355,7 @@ static void falc_intr(pc300_t * card)
|
||||
static irqreturn_t cpc_intr(int irq, void *dev_id)
|
||||
{
|
||||
pc300_t *card = dev_id;
|
||||
volatile ucchar plx_status;
|
||||
volatile u8 plx_status;
|
||||
|
||||
if (!card) {
|
||||
#ifdef PC300_DEBUG_INTR
|
||||
@ -2394,7 +2394,7 @@ static irqreturn_t cpc_intr(int irq, void *dev_id)
|
||||
|
||||
static void cpc_sca_status(pc300_t * card, int ch)
|
||||
{
|
||||
ucchar ilar;
|
||||
u8 ilar;
|
||||
void __iomem *scabase = card->hw.scabase;
|
||||
unsigned long flags;
|
||||
|
||||
@ -2812,7 +2812,7 @@ static int cpc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
|
||||
}
|
||||
}
|
||||
|
||||
static int clock_rate_calc(uclong rate, uclong clock, int *br_io)
|
||||
static int clock_rate_calc(u32 rate, u32 clock, int *br_io)
|
||||
{
|
||||
int br, tc;
|
||||
int br_pwr, error;
|
||||
@ -2849,11 +2849,11 @@ static int ch_config(pc300dev_t * d)
|
||||
void __iomem *scabase = card->hw.scabase;
|
||||
void __iomem *plxbase = card->hw.plxbase;
|
||||
int ch = chan->channel;
|
||||
uclong clkrate = chan->conf.phys_settings.clock_rate;
|
||||
uclong clktype = chan->conf.phys_settings.clock_type;
|
||||
ucshort encoding = chan->conf.proto_settings.encoding;
|
||||
ucshort parity = chan->conf.proto_settings.parity;
|
||||
ucchar md0, md2;
|
||||
u32 clkrate = chan->conf.phys_settings.clock_rate;
|
||||
u32 clktype = chan->conf.phys_settings.clock_type;
|
||||
u16 encoding = chan->conf.proto_settings.encoding;
|
||||
u16 parity = chan->conf.proto_settings.parity;
|
||||
u8 md0, md2;
|
||||
|
||||
/* Reset the channel */
|
||||
cpc_writeb(scabase + M_REG(CMD, ch), CMD_CH_RST);
|
||||
@ -3193,16 +3193,16 @@ static int cpc_close(struct net_device *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static uclong detect_ram(pc300_t * card)
|
||||
static u32 detect_ram(pc300_t * card)
|
||||
{
|
||||
uclong i;
|
||||
ucchar data;
|
||||
u32 i;
|
||||
u8 data;
|
||||
void __iomem *rambase = card->hw.rambase;
|
||||
|
||||
card->hw.ramsize = PC300_RAMSIZE;
|
||||
/* Let's find out how much RAM is present on this board */
|
||||
for (i = 0; i < card->hw.ramsize; i++) {
|
||||
data = (ucchar) (i & 0xff);
|
||||
data = (u8)(i & 0xff);
|
||||
cpc_writeb(rambase + i, data);
|
||||
if (cpc_readb(rambase + i) != data) {
|
||||
break;
|
||||
@ -3279,7 +3279,7 @@ static void cpc_init_card(pc300_t * card)
|
||||
cpc_writeb(card->hw.scabase + DMER, 0x80);
|
||||
|
||||
if (card->hw.type == PC300_TE) {
|
||||
ucchar reg1;
|
||||
u8 reg1;
|
||||
|
||||
/* Check CPLD version */
|
||||
reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
|
||||
@ -3413,7 +3413,7 @@ cpc_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
{
|
||||
static int first_time = 1;
|
||||
int err, eeprom_outdated = 0;
|
||||
ucshort device_id;
|
||||
u16 device_id;
|
||||
pc300_t *card;
|
||||
|
||||
if (first_time) {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user