Minki/linux
1
0
Fork 1
mirror of https://github.com/torvalds/linux.git synced 2024-12-12 22:23:55 +00:00
Code Issues Packages Projects Releases Wiki Activity

x86/cpu: Init AP exception handling from cpu_init_secondary()

Browse Source 
SEV-ES guests require properly setup task register with which the TSS
descriptor in the GDT can be located so that the IST-type #VC exception
handler which they need to function properly, can be executed.

This setup needs to happen before attempting to load microcode in
ucode_cpu_init() on secondary CPUs which can cause such #VC exceptions.

Simplify the machinery by running that exception setup from a new function
cpu_init_secondary() and explicitly call cpu_init_exception_handling() for
the boot CPU before cpu_init(). The latter prepares for fixing and
simplifying the exception/IST setup on the boot CPU.

There should be no functional changes resulting from this patch.

[ tglx: Reworked it so cpu_init_exception_handling() stays seperate ]

Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Lai Jiangshan <laijs@linux.alibaba.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>                                                                                                                                                                                                                        
Link: https://lore.kernel.org/r/87k0o6gtvu.ffs@nanos.tec.linutronix.de
This commit is contained in:
Borislav Petkov 2021-05-10 23:29:25 +02:00 committed by Thomas Gleixner
parent d07f6ca923
commit b1efd0ff4b
4 changed files with 18 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/x86/include/asm/processor.h
View File

@ -663,6 +663,7 @@ extern void load_direct_gdt(int);
extern void load_fixmap_gdt(int);
extern void load_percpu_segment(int);
extern void cpu_init(void);
extern void cpu_init_secondary(void);
extern void cpu_init_exception_handling(void);
extern void cr4_init(void);

28
arch/x86/kernel/cpu/common.c
View File

@ -1938,13 +1938,12 @@ void cpu_init_exception_handling(void)
/*
* cpu_init() initializes state that is per-CPU. Some data is already
* initialized (naturally) in the bootstrap process, such as the GDT
* and IDT. We reload them nevertheless, this function acts as a
* 'CPU state barrier', nothing should get across.
* initialized (naturally) in the bootstrap process, such as the GDT. We
* reload it nevertheless, this function acts as a 'CPU state barrier',
* nothing should get across.
*/
void cpu_init(void)
{
struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
struct task_struct *cur = current;
int cpu = raw_smp_processor_id();
@ -1957,8 +1956,6 @@ void cpu_init(void)
early_cpu_to_node(cpu) != NUMA_NO_NODE)
set_numa_node(early_cpu_to_node(cpu));
#endif
setup_getcpu(cpu);
pr_debug("Initializing CPU#%d\n", cpu);
if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
@ -1970,7 +1967,6 @@ void cpu_init(void)
* and set up the GDT descriptor:
*/
switch_to_new_gdt(cpu);
load_current_idt();
if (IS_ENABLED(CONFIG_X86_64)) {
loadsegment(fs, 0);
@ -1990,12 +1986,6 @@ void cpu_init(void)
initialize_tlbstate_and_flush();
enter_lazy_tlb(&init_mm, cur);
/* Initialize the TSS. */
tss_setup_ist(tss);
tss_setup_io_bitmap(tss);
set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
load_TR_desc();
/*
* sp0 points to the entry trampoline stack regardless of what task
* is running.
@ -2017,6 +2007,18 @@ void cpu_init(void)
load_fixmap_gdt(cpu);
}
#ifdef CONFIG_SMP
void cpu_init_secondary(void)
{
/*
* Relies on the BP having set-up the IDT tables, which are loaded
* on this CPU in cpu_init_exception_handling().
*/
cpu_init_exception_handling();
cpu_init();
}
#endif
/*
* The microcode loader calls this upon late microcode load to recheck features,
* only when microcode has been updated. Caller holds microcode_mutex and CPU

3
arch/x86/kernel/smpboot.c
View File

@ -232,8 +232,7 @@ static void notrace start_secondary(void *unused)
load_cr3(swapper_pg_dir);
__flush_tlb_all();
#endif
cpu_init_exception_handling();
cpu_init();
cpu_init_secondary();
rcu_cpu_starting(raw_smp_processor_id());
x86_cpuinit.early_percpu_clock_init();
preempt_disable();

4
arch/x86/kernel/traps.c
View File

@ -1162,9 +1162,7 @@ void __init trap_init(void)
idt_setup_traps();
/*
* Should be a barrier for any external CPU state:
*/
cpu_init_exception_handling();
cpu_init();
idt_setup_ist_traps();