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staging: r8188eu: Add files for new driver - part 22
This commit adds files include/Hal8188EFWImg_CE.h, include/Hal8188EPhyCfg.h, include/Hal8188EPhyReg.h, include/Hal8188EPwrSeq.h, include/Hal8188ERateAdaptive.h, include/Hal8188EReg.h, include/HalHWImg8188E_BB.h, include/HalHWImg8188E_FW.h, include/HalHWImg8188E_MAC.h, include/HalHWImg8188E_RF.h, include/HalPhyRf.h, include/HalPhyRf_8188e.h, include/HalPwrSeqCmd.h, and include/HalVerDef.h. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Larry Finger
Greg Kroah-Hartman
parent
a7c947b7f3
commit
b1da99bbf2
28
drivers/staging/rtl8188eu/include/Hal8188EFWImg_CE.h
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28
drivers/staging/rtl8188eu/include/Hal8188EFWImg_CE.h
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@ -0,0 +1,28 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __INC_HAL8188E_FW_IMG_H
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#define __INC_HAL8188E_FW_IMG_H
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/* V10(1641) */
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#define Rtl8188EFWImgArrayLength 13904
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extern const u8 Rtl8188EFwImgArray[Rtl8188EFWImgArrayLength];
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#endif /* __INC_HAL8188E_FW_IMG_H */
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276
drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h
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276
drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h
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@ -0,0 +1,276 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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*
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*
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******************************************************************************/
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#ifndef __INC_HAL8188EPHYCFG_H__
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#define __INC_HAL8188EPHYCFG_H__
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/*--------------------------Define Parameters-------------------------------*/
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50 /* us */
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#define AntennaDiversityValue 0x80
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#define MAX_TXPWR_IDX_NMODE_92S 63
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#define Reset_Cnt_Limit 3
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#define IQK_MAC_REG_NUM 4
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#define IQK_ADDA_REG_NUM 16
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#define IQK_BB_REG_NUM 9
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#define HP_THERMAL_NUM 8
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#define MAX_AGGR_NUM 0x07
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/*--------------------------Define Parameters-------------------------------*/
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/*------------------------------Define structure----------------------------*/
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enum sw_chnl_cmd_id {
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CmdID_End,
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CmdID_SetTxPowerLevel,
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CmdID_BBRegWrite10,
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CmdID_WritePortUlong,
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CmdID_WritePortUshort,
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CmdID_WritePortUchar,
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CmdID_RF_WriteReg,
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};
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/* 1. Switch channel related */
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struct sw_chnl_cmd {
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enum sw_chnl_cmd_id CmdID;
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u32 Para1;
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u32 Para2;
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u32 msDelay;
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};
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enum hw90_block {
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HW90_BLOCK_MAC = 0,
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HW90_BLOCK_PHY0 = 1,
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HW90_BLOCK_PHY1 = 2,
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HW90_BLOCK_RF = 3,
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HW90_BLOCK_MAXIMUM = 4, /* Never use this */
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};
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enum rf_radio_path {
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RF_PATH_A = 0, /* Radio Path A */
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RF_PATH_B = 1, /* Radio Path B */
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RF_PATH_C = 2, /* Radio Path C */
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RF_PATH_D = 3, /* Radio Path D */
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};
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#define MAX_PG_GROUP 13
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#define RF_PATH_MAX 2
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#define MAX_RF_PATH RF_PATH_MAX
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#define MAX_TX_COUNT 4 /* path numbers */
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#define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */
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#define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8,
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*ch9~11, ch12~13, CH 14
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* total three groups */
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#define CHANNEL_GROUP_MAX_88E 6
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enum wireless_mode {
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WIRELESS_MODE_UNKNOWN = 0x00,
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WIRELESS_MODE_A = BIT2,
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WIRELESS_MODE_B = BIT0,
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WIRELESS_MODE_G = BIT1,
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WIRELESS_MODE_AUTO = BIT5,
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WIRELESS_MODE_N_24G = BIT3,
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WIRELESS_MODE_N_5G = BIT4,
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WIRELESS_MODE_AC = BIT6
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};
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enum phy_rate_tx_offset_area {
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RA_OFFSET_LEGACY_OFDM1,
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RA_OFFSET_LEGACY_OFDM2,
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RA_OFFSET_HT_OFDM1,
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RA_OFFSET_HT_OFDM2,
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RA_OFFSET_HT_OFDM3,
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RA_OFFSET_HT_OFDM4,
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RA_OFFSET_HT_CCK,
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};
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/* BB/RF related */
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enum RF_TYPE_8190P {
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RF_TYPE_MIN, /* 0 */
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RF_8225 = 1, /* 1 11b/g RF for verification only */
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RF_8256 = 2, /* 2 11b/g/n */
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RF_8258 = 3, /* 3 11a/b/g/n RF */
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RF_6052 = 4, /* 4 11b/g/n RF */
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/* TODO: We should remove this psudo PHY RF after we get new RF. */
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RF_PSEUDO_11N = 5, /* 5, It is a temporality RF. */
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};
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struct bb_reg_def {
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u32 rfintfs; /* set software control: */
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/* 0x870~0x877[8 bytes] */
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u32 rfintfi; /* readback data: */
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/* 0x8e0~0x8e7[8 bytes] */
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u32 rfintfo; /* output data: */
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/* 0x860~0x86f [16 bytes] */
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u32 rfintfe; /* output enable: */
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/* 0x860~0x86f [16 bytes] */
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u32 rf3wireOffset; /* LSSI data: */
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/* 0x840~0x84f [16 bytes] */
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u32 rfLSSI_Select; /* BB Band Select: */
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/* 0x878~0x87f [8 bytes] */
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u32 rfTxGainStage; /* Tx gain stage: */
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/* 0x80c~0x80f [4 bytes] */
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u32 rfHSSIPara1; /* wire parameter control1 : */
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/* 0x820~0x823,0x828~0x82b,
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* 0x830~0x833, 0x838~0x83b [16 bytes] */
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u32 rfHSSIPara2; /* wire parameter control2 : */
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/* 0x824~0x827,0x82c~0x82f, 0x834~0x837,
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* 0x83c~0x83f [16 bytes] */
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u32 rfSwitchControl; /* Tx Rx antenna control : */
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/* 0x858~0x85f [16 bytes] */
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u32 rfAGCControl1; /* AGC parameter control1 : */
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/* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
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* 0xc68~0xc6b [16 bytes] */
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u32 rfAGCControl2; /* AGC parameter control2 : */
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/* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
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* 0xc6c~0xc6f [16 bytes] */
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u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */
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/* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
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* 0xc2c~0xc2f [16 bytes] */
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u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter,
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* Rx DC notch filter : */
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/* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
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* 0xc28~0xc2b [16 bytes] */
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u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */
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/* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
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* 0xc98~0xc9b [16 bytes] */
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u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */
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/* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
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* 0xc9c~0xc9f [16 bytes] */
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u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */
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/* 0x8a0~0x8af [16 bytes] */
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u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for
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* Path A and B */
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};
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struct ant_sel_ofdm {
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u32 r_tx_antenna:4;
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u32 r_ant_l:4;
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u32 r_ant_non_ht:4;
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u32 r_ant_ht1:4;
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u32 r_ant_ht2:4;
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u32 r_ant_ht_s1:4;
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u32 r_ant_non_ht_s1:4;
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u32 OFDM_TXSC:2;
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u32 reserved:2;
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};
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struct ant_sel_cck {
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u8 r_cckrx_enable_2:2;
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u8 r_cckrx_enable:2;
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u8 r_ccktx_enable:4;
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};
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/*------------------------------Define structure----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export global variable----------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*------------------------Export Marco Definition---------------------------*/
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/*--------------------------Exported Function prototype---------------------*/
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/* */
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/* BB and RF register read/write */
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/* */
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u32 rtl8188e_PHY_QueryBBReg(struct adapter *adapter, u32 regaddr, u32 mask);
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void rtl8188e_PHY_SetBBReg(struct adapter *Adapter, u32 RegAddr,
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u32 mask, u32 data);
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u32 rtl8188e_PHY_QueryRFReg(struct adapter *adapter, enum rf_radio_path rfpath,
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u32 regaddr, u32 mask);
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void rtl8188e_PHY_SetRFReg(struct adapter *adapter, enum rf_radio_path rfpath,
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u32 regaddr, u32 mask, u32 data);
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/* Initialization related function */
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/* MAC/BB/RF HAL config */
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int PHY_MACConfig8188E(struct adapter *adapter);
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int PHY_BBConfig8188E(struct adapter *adapter);
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int PHY_RFConfig8188E(struct adapter *adapter);
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/* RF config */
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int rtl8188e_PHY_ConfigRFWithParaFile(struct adapter *adapter, u8 *filename,
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enum rf_radio_path rfpath);
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int rtl8188e_PHY_ConfigRFWithHeaderFile(struct adapter *adapter,
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enum rf_radio_path rfpath);
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/* Read initi reg value for tx power setting. */
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void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);
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/* BB TX Power R/W */
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void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel);
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void PHY_SetTxPowerLevel8188E(struct adapter *adapter, u8 channel);
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bool PHY_UpdateTxPowerDbm8188E(struct adapter *adapter, int power);
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void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
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/* Switch bandwidth for 8192S */
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void PHY_SetBWMode8188E(struct adapter *adapter,
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enum ht_channel_width chnlwidth, unsigned char offset);
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/* channel switch related funciton */
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void PHY_SwChnl8188E(struct adapter *adapter, u8 channel);
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/* Call after initialization */
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void ChkFwCmdIoDone(struct adapter *adapter);
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/* BB/MAC/RF other monitor API */
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void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main);
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void PHY_SwitchEphyParameter(struct adapter *adapter);
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void PHY_EnableHostClkReq(struct adapter *adapter);
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bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);
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void storePwrIndexDiffRateOffset(struct adapter *adapter, u32 regaddr,
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u32 mask, u32 data);
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/*--------------------------Exported Function prototype---------------------*/
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#define PHY_QueryBBReg(adapt, regaddr, mask) \
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rtl8188e_PHY_QueryBBReg((adapt), (regaddr), (mask))
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#define PHY_SetBBReg(adapt, regaddr, bitmask, data) \
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rtl8188e_PHY_SetBBReg((adapt), (regaddr), (bitmask), (data))
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#define PHY_QueryRFReg(adapt, rfpath, regaddr, bitmask) \
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rtl8188e_PHY_QueryRFReg((adapt), (rfpath), (regaddr), (bitmask))
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#define PHY_SetRFReg(adapt, rfpath, regaddr, bitmask, data) \
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rtl8188e_PHY_SetRFReg((adapt), (rfpath), (regaddr), (bitmask), (data))
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#define PHY_SetMacReg PHY_SetBBReg
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#define SIC_HW_SUPPORT 0
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#define SIC_MAX_POLL_CNT 5
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#define SIC_CMD_READY 0
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#define SIC_CMD_WRITE 1
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#define SIC_CMD_READ 2
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#define SIC_CMD_REG 0x1EB /* 1byte */
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#define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */
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#define SIC_DATA_REG 0x1EC /* 1bc~1bf */
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#endif /* __INC_HAL8192CPHYCFG_H */
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1094
drivers/staging/rtl8188eu/include/Hal8188EPhyReg.h
Normal file
1094
drivers/staging/rtl8188eu/include/Hal8188EPhyReg.h
Normal file
File diff suppressed because it is too large
Load Diff
176
drivers/staging/rtl8188eu/include/Hal8188EPwrSeq.h
Normal file
176
drivers/staging/rtl8188eu/include/Hal8188EPwrSeq.h
Normal file
@ -0,0 +1,176 @@
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
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* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
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*
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*
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******************************************************************************/
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#ifndef __HAL8188EPWRSEQ_H__
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#define __HAL8188EPWRSEQ_H__
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#include "HalPwrSeqCmd.h"
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/*
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Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
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There are 6 HW Power States:
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0: POFF--Power Off
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1: PDN--Power Down
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2: CARDEMU--Card Emulation
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3: ACT--Active Mode
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4: LPS--Low Power State
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5: SUS--Suspend
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The transision from different states are defined below
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TRANS_CARDEMU_TO_ACT
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TRANS_ACT_TO_CARDEMU
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TRANS_CARDEMU_TO_SUS
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TRANS_SUS_TO_CARDEMU
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TRANS_CARDEMU_TO_PDN
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TRANS_ACT_TO_LPS
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TRANS_LPS_TO_ACT
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TRANS_END
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PWR SEQ Version: rtl8188E_PwrSeq_V09.h
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*/
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#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
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#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
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#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
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#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
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#define RTL8188E_TRANS_END_STEPS 1
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#define RTL8188E_TRANS_CARDEMU_TO_ACT \
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/* format */ \
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/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
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{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, /* 0x02[1:0] = 0 reset BB*/ \
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{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, /* 0x04[15] = 0 disable HWPDN (control by DRV)*/\
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, /*0x04[12:11] = 2b'00 disable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x04[8] = 1 polling until return 0*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, /*wait till 0x04[8] = 0*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*LDO normal mode*/ \
|
||||
{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*SDIO Driving*/ \
|
||||
|
||||
#define RTL8188E_TRANS_ACT_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0},/*0x1F[7:0] = 0 turn off RF*/ \
|
||||
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*LDO Sleep mode*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 turn off MAC by HW state machine*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x04[9] = 0 polling until return 0 to disable*/ \
|
||||
|
||||
#define RTL8188E_TRANS_CARDEMU_TO_SUS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01enable WL suspend*/ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*0x04[12:11] = 2b'11enable WL suspend for PCIe*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, BIT7}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
|
||||
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
|
||||
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8188E_TRANS_SUS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, /*0x24[23] = 2b'01 schmit trigger */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
|
||||
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */ \
|
||||
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*Clear SIC_EN register 0x40[12] = 1'b0 */ \
|
||||
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*Set USB suspend enable local register 0xfe10[4]=1 */ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power state to suspend*/
|
||||
|
||||
#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, /*Set SDIO suspend local register*/ \
|
||||
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power state to suspend*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, /*0x04[12:11] = 2b'01enable WL suspend*/
|
||||
|
||||
#define RTL8188E_TRANS_CARDEMU_TO_PDN \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* 0x04[16] = 0*/\
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
|
||||
|
||||
#define RTL8188E_TRANS_PDN_TO_CARDEMU \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here */ \
|
||||
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
|
||||
|
||||
/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
|
||||
#define RTL8188E_TRANS_ACT_TO_LPS \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here */ \
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
|
||||
{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0},/*Should be zero if no packet is transmitting*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/*CCK and OFDM are disabled,and clock are gated*/ \
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US},/*Delay 1us*/ \
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/ \
|
||||
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5},/*Respond TxOK to scheduler*/ \
|
||||
|
||||
|
||||
#define RTL8188E_TRANS_LPS_TO_ACT \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here */ \
|
||||
{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84}, /*SDIO RPWM*/\
|
||||
{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*USB RPWM*/\
|
||||
{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84}, /*PCIe RPWM*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/\
|
||||
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*. 0x08[4] = 0 switch TSF to 40M*/\
|
||||
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]=0 TSF in 40M*/\
|
||||
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
|
||||
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*. 0x101[1] = 1*/\
|
||||
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, /*. 0x100[7:0] = 0xFF enable WMAC TRX*/\
|
||||
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, /*. 0x02[1:0] = 2b'11 enable BB macro*/\
|
||||
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
|
||||
|
||||
#define RTL8188E_TRANS_END \
|
||||
/* format */ \
|
||||
/* { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value }, comments here*/ \
|
||||
{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,0, PWR_CMD_END, 0, 0}, /* */
|
||||
|
||||
|
||||
extern struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
|
||||
extern struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_END_STEPS];
|
||||
extern struct wl_pwr_cfg rtl8188E_card_disable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
|
||||
extern struct wl_pwr_cfg rtl8188E_card_enable_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
|
||||
extern struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
|
||||
extern struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS+RTL8188E_TRANS_END_STEPS];
|
||||
extern struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS+RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS+RTL8188E_TRANS_END_STEPS];
|
||||
extern struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS+RTL8188E_TRANS_END_STEPS];
|
||||
extern struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS+RTL8188E_TRANS_END_STEPS];
|
||||
|
||||
#endif /* __HAL8188EPWRSEQ_H__ */
|
||||
75
drivers/staging/rtl8188eu/include/Hal8188ERateAdaptive.h
Normal file
75
drivers/staging/rtl8188eu/include/Hal8188ERateAdaptive.h
Normal file
@ -0,0 +1,75 @@
|
||||
#ifndef __INC_RA_H
|
||||
#define __INC_RA_H
|
||||
/*++
|
||||
Copyright (c) Realtek Semiconductor Corp. All rights reserved.
|
||||
|
||||
Module Name:
|
||||
RateAdaptive.h
|
||||
|
||||
Abstract:
|
||||
Prototype of RA and related data structure.
|
||||
|
||||
Major Change History:
|
||||
When Who What
|
||||
---------- --------------- -------------------------------
|
||||
2011-08-12 Page Create.
|
||||
--*/
|
||||
|
||||
/* Rate adaptive define */
|
||||
#define PERENTRY 23
|
||||
#define RETRYSIZE 5
|
||||
#define RATESIZE 28
|
||||
#define TX_RPT2_ITEM_SIZE 8
|
||||
|
||||
/* */
|
||||
/* TX report 2 format in Rx desc */
|
||||
/* */
|
||||
#define GET_TX_RPT2_DESC_PKT_LEN_88E(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc, 0, 9)
|
||||
#define GET_TX_RPT2_DESC_MACID_VALID_1_88E(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+16, 0, 32)
|
||||
#define GET_TX_RPT2_DESC_MACID_VALID_2_88E(__pRxStatusDesc) \
|
||||
LE_BITS_TO_4BYTE(__pRxStatusDesc+20, 0, 32)
|
||||
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_0(__pAddr) \
|
||||
LE_BITS_TO_4BYTE(__pAddr, 0, 16)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_1(__pAddr) \
|
||||
LE_BITS_TO_1BYTE(__pAddr+2, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_2(__pAddr) \
|
||||
LE_BITS_TO_1BYTE(__pAddr+3, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_3(__pAddr) \
|
||||
LE_BITS_TO_1BYTE(__pAddr+4, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_RERTY_4(__pAddr) \
|
||||
LE_BITS_TO_1BYTE(__pAddr+4+1, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_DROP_0(__pAddr) \
|
||||
LE_BITS_TO_1BYTE(__pAddr+4+2, 0, 8)
|
||||
#define GET_TX_REPORT_TYPE1_DROP_1(__pAddr) \
|
||||
LE_BITS_TO_1BYTE(__pAddr+4+3, 0, 8)
|
||||
|
||||
/* End rate adaptive define */
|
||||
|
||||
void ODM_RASupport_Init(struct odm_dm_struct *dm_odm);
|
||||
|
||||
int ODM_RAInfo_Init_all(struct odm_dm_struct *dm_odm);
|
||||
|
||||
int ODM_RAInfo_Init(struct odm_dm_struct *dm_odm, u8 MacID);
|
||||
|
||||
u8 ODM_RA_GetShortGI_8188E(struct odm_dm_struct *dm_odm, u8 MacID);
|
||||
|
||||
u8 ODM_RA_GetDecisionRate_8188E(struct odm_dm_struct *dm_odm, u8 MacID);
|
||||
|
||||
u8 ODM_RA_GetHwPwrStatus_8188E(struct odm_dm_struct *dm_odm, u8 MacID);
|
||||
void ODM_RA_UpdateRateInfo_8188E(struct odm_dm_struct *dm_odm, u8 MacID,
|
||||
u8 RateID, u32 RateMask,
|
||||
u8 SGIEnable);
|
||||
|
||||
void ODM_RA_SetRSSI_8188E(struct odm_dm_struct *dm_odm, u8 macid,
|
||||
u8 rssi);
|
||||
|
||||
void ODM_RA_TxRPT2Handle_8188E(struct odm_dm_struct *dm_odm,
|
||||
u8 *txrpt_buf, u16 txrpt_len,
|
||||
u32 validentry0, u32 validentry1);
|
||||
|
||||
void ODM_RA_Set_TxRPT_Time(struct odm_dm_struct *dm_odm, u16 minRptTime);
|
||||
|
||||
#endif
|
||||
46
drivers/staging/rtl8188eu/include/Hal8188EReg.h
Normal file
46
drivers/staging/rtl8188eu/include/Hal8188EReg.h
Normal file
@ -0,0 +1,46 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
/* */
|
||||
/* File Name: Hal8188EReg.h */
|
||||
/* */
|
||||
/* Description: */
|
||||
/* */
|
||||
/* This file is for RTL8188E register definition. */
|
||||
/* */
|
||||
/* */
|
||||
/* */
|
||||
#ifndef __HAL_8188E_REG_H__
|
||||
#define __HAL_8188E_REG_H__
|
||||
|
||||
/* */
|
||||
/* Register Definition */
|
||||
/* */
|
||||
#define TRX_ANTDIV_PATH 0x860
|
||||
#define RX_ANTDIV_PATH 0xb2c
|
||||
#define ODM_R_A_AGC_CORE1_8188E 0xc50
|
||||
|
||||
|
||||
/* */
|
||||
/* Bitmap Definition */
|
||||
/* */
|
||||
#define BIT_FA_RESET_8188E BIT0
|
||||
|
||||
|
||||
#endif
|
||||
44
drivers/staging/rtl8188eu/include/HalHWImg8188E_BB.h
Normal file
44
drivers/staging/rtl8188eu/include/HalHWImg8188E_BB.h
Normal file
@ -0,0 +1,44 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_BB_8188E_HW_IMG_H
|
||||
#define __INC_BB_8188E_HW_IMG_H
|
||||
|
||||
/* static bool CheckCondition(const u32 Condition, const u32 Hex); */
|
||||
|
||||
/******************************************************************************
|
||||
* AGC_TAB_1T.TXT
|
||||
******************************************************************************/
|
||||
|
||||
enum HAL_STATUS ODM_ReadAndConfig_AGC_TAB_1T_8188E(struct odm_dm_struct *odm);
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG_1T.TXT
|
||||
******************************************************************************/
|
||||
|
||||
enum HAL_STATUS ODM_ReadAndConfig_PHY_REG_1T_8188E(struct odm_dm_struct *odm);
|
||||
|
||||
/******************************************************************************
|
||||
* PHY_REG_PG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
void ODM_ReadAndConfig_PHY_REG_PG_8188E(struct odm_dm_struct *dm_odm);
|
||||
|
||||
#endif
|
||||
34
drivers/staging/rtl8188eu/include/HalHWImg8188E_FW.h
Normal file
34
drivers/staging/rtl8188eu/include/HalHWImg8188E_FW.h
Normal file
@ -0,0 +1,34 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_FW_8188E_HW_IMG_H
|
||||
#define __INC_FW_8188E_HW_IMG_H
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* FW_AP.TXT
|
||||
******************************************************************************/
|
||||
/******************************************************************************
|
||||
* FW_WoWLAN.TXT
|
||||
******************************************************************************/
|
||||
#define ArrayLength_8188E_FW_WoWLAN 15764
|
||||
extern const u8 Array_8188E_FW_WoWLAN[ArrayLength_8188E_FW_WoWLAN];
|
||||
|
||||
#endif
|
||||
30
drivers/staging/rtl8188eu/include/HalHWImg8188E_MAC.h
Normal file
30
drivers/staging/rtl8188eu/include/HalHWImg8188E_MAC.h
Normal file
@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_MAC_8188E_HW_IMG_H
|
||||
#define __INC_MAC_8188E_HW_IMG_H
|
||||
|
||||
/******************************************************************************
|
||||
* MAC_REG.TXT
|
||||
******************************************************************************/
|
||||
|
||||
enum HAL_STATUS ODM_ReadAndConfig_MAC_REG_8188E(struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT */
|
||||
30
drivers/staging/rtl8188eu/include/HalHWImg8188E_RF.h
Normal file
30
drivers/staging/rtl8188eu/include/HalHWImg8188E_RF.h
Normal file
@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __INC_RF_8188E_HW_IMG_H
|
||||
#define __INC_RF_8188E_HW_IMG_H
|
||||
|
||||
/******************************************************************************
|
||||
* RadioA_1T.TXT
|
||||
******************************************************************************/
|
||||
|
||||
enum HAL_STATUS ODM_ReadAndConfig_RadioA_1T_8188E(struct odm_dm_struct *odm);
|
||||
|
||||
#endif /* end of HWIMG_SUPPORT */
|
||||
30
drivers/staging/rtl8188eu/include/HalPhyRf.h
Normal file
30
drivers/staging/rtl8188eu/include/HalPhyRf.h
Normal file
@ -0,0 +1,30 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_H__
|
||||
#define __HAL_PHY_RF_H__
|
||||
|
||||
#define ODM_TARGET_CHNL_NUM_2G_5G 59
|
||||
|
||||
void ODM_ResetIQKResult(struct odm_dm_struct *pDM_Odm);
|
||||
|
||||
u8 ODM_GetRightChnlPlaceforIQK(u8 chnl);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_H__ */
|
||||
63
drivers/staging/rtl8188eu/include/HalPhyRf_8188e.h
Normal file
63
drivers/staging/rtl8188eu/include/HalPhyRf_8188e.h
Normal file
@ -0,0 +1,63 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __HAL_PHY_RF_8188E_H__
|
||||
#define __HAL_PHY_RF_8188E_H__
|
||||
|
||||
/*--------------------------Define Parameters-------------------------------*/
|
||||
#define IQK_DELAY_TIME_88E 10 /* ms */
|
||||
#define index_mapping_NUM_88E 15
|
||||
#define AVG_THERMAL_NUM_88E 4
|
||||
|
||||
|
||||
void ODM_TxPwrTrackAdjust88E(struct odm_dm_struct *pDM_Odm,
|
||||
u8 Type, /* 0 = OFDM, 1 = CCK */
|
||||
u8 *pDirection,/* 1 = +(incr) 2 = -(decr) */
|
||||
u32 *pOutWriteVal); /* Tx tracking CCK/OFDM BB
|
||||
* swing index adjust */
|
||||
|
||||
|
||||
void odm_TXPowerTrackingCallback_ThermalMeter_8188E(struct adapter *Adapter);
|
||||
|
||||
|
||||
/* 1 7. IQK */
|
||||
|
||||
void PHY_IQCalibrate_8188E(struct adapter *Adapter, bool ReCovery);
|
||||
|
||||
/* LC calibrate */
|
||||
void PHY_LCCalibrate_8188E(struct adapter *pAdapter);
|
||||
|
||||
/* AP calibrate */
|
||||
void PHY_APCalibrate_8188E(struct adapter *pAdapter, s8 delta);
|
||||
|
||||
void PHY_DigitalPredistortion_8188E(struct adapter *pAdapter);
|
||||
|
||||
void _PHY_SaveADDARegisters(struct adapter *pAdapter, u32 *ADDAReg,
|
||||
u32 *ADDABackup, u32 RegisterNum);
|
||||
|
||||
void _PHY_PathADDAOn(struct adapter *pAdapter, u32 *ADDAReg,
|
||||
bool isPathAOn, bool is2T);
|
||||
|
||||
void _PHY_MACSettingCalibration(struct adapter *pAdapter, u32 *MACReg,
|
||||
u32 *MACBackup);
|
||||
|
||||
void _PHY_PathAStandBy(struct adapter *pAdapter);
|
||||
|
||||
#endif /* #ifndef __HAL_PHY_RF_8188E_H__ */
|
||||
128
drivers/staging/rtl8188eu/include/HalPwrSeqCmd.h
Normal file
128
drivers/staging/rtl8188eu/include/HalPwrSeqCmd.h
Normal file
@ -0,0 +1,128 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __HALPWRSEQCMD_H__
|
||||
#define __HALPWRSEQCMD_H__
|
||||
|
||||
#include <drv_types.h>
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of cmd: 4 bits */
|
||||
/*---------------------------------------------*/
|
||||
#define PWR_CMD_READ 0x00
|
||||
/* offset: the read register offset */
|
||||
/* msk: the mask of the read value */
|
||||
/* value: N/A, left by 0 */
|
||||
/* note: dirver shall implement this function by read & msk */
|
||||
|
||||
#define PWR_CMD_WRITE 0x01
|
||||
/* offset: the read register offset */
|
||||
/* msk: the mask of the write bits */
|
||||
/* value: write value */
|
||||
/* note: driver shall implement this cmd by read & msk after write */
|
||||
|
||||
#define PWR_CMD_POLLING 0x02
|
||||
/* offset: the read register offset */
|
||||
/* msk: the mask of the polled value */
|
||||
/* value: the value to be polled, masked by the msd field. */
|
||||
/* note: driver shall implement this cmd by */
|
||||
/* do{ */
|
||||
/* if ( (Read(offset) & msk) == (value & msk) ) */
|
||||
/* break; */
|
||||
/* } while (not timeout); */
|
||||
|
||||
#define PWR_CMD_DELAY 0x03
|
||||
/* offset: the value to delay */
|
||||
/* msk: N/A */
|
||||
/* value: the unit of delay, 0: us, 1: ms */
|
||||
|
||||
#define PWR_CMD_END 0x04
|
||||
/* offset: N/A */
|
||||
/* msk: N/A */
|
||||
/* value: N/A */
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of base: 4 bits */
|
||||
/*---------------------------------------------*/
|
||||
/* define the base address of each block */
|
||||
#define PWR_BASEADDR_MAC 0x00
|
||||
#define PWR_BASEADDR_USB 0x01
|
||||
#define PWR_BASEADDR_PCIE 0x02
|
||||
#define PWR_BASEADDR_SDIO 0x03
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of interface_msk: 4 bits */
|
||||
/*---------------------------------------------*/
|
||||
#define PWR_INTF_SDIO_MSK BIT(0)
|
||||
#define PWR_INTF_USB_MSK BIT(1)
|
||||
#define PWR_INTF_PCI_MSK BIT(2)
|
||||
#define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of fab_msk: 4 bits */
|
||||
/*---------------------------------------------*/
|
||||
#define PWR_FAB_TSMC_MSK BIT(0)
|
||||
#define PWR_FAB_UMC_MSK BIT(1)
|
||||
#define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
|
||||
|
||||
/*---------------------------------------------*/
|
||||
/* 3 The value of cut_msk: 8 bits */
|
||||
/*---------------------------------------------*/
|
||||
#define PWR_CUT_TESTCHIP_MSK BIT(0)
|
||||
#define PWR_CUT_A_MSK BIT(1)
|
||||
#define PWR_CUT_B_MSK BIT(2)
|
||||
#define PWR_CUT_C_MSK BIT(3)
|
||||
#define PWR_CUT_D_MSK BIT(4)
|
||||
#define PWR_CUT_E_MSK BIT(5)
|
||||
#define PWR_CUT_F_MSK BIT(6)
|
||||
#define PWR_CUT_G_MSK BIT(7)
|
||||
#define PWR_CUT_ALL_MSK 0xFF
|
||||
|
||||
|
||||
enum pwrseq_cmd_delat_unit {
|
||||
PWRSEQ_DELAY_US,
|
||||
PWRSEQ_DELAY_MS,
|
||||
};
|
||||
|
||||
struct wl_pwr_cfg {
|
||||
u16 offset;
|
||||
u8 cut_msk;
|
||||
u8 fab_msk:4;
|
||||
u8 interface_msk:4;
|
||||
u8 base:4;
|
||||
u8 cmd:4;
|
||||
u8 msk;
|
||||
u8 value;
|
||||
};
|
||||
|
||||
#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
|
||||
#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
|
||||
#define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
|
||||
#define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
|
||||
#define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
|
||||
#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
|
||||
#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
|
||||
#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
|
||||
|
||||
|
||||
/* Prototype of protected function. */
|
||||
u8 HalPwrSeqCmdParsing(struct adapter *padapter, u8 CutVersion, u8 FabVersion,
|
||||
u8 InterfaceType, struct wl_pwr_cfg PwrCfgCmd[]);
|
||||
|
||||
#endif
|
||||
167
drivers/staging/rtl8188eu/include/HalVerDef.h
Normal file
167
drivers/staging/rtl8188eu/include/HalVerDef.h
Normal file
@ -0,0 +1,167 @@
|
||||
/******************************************************************************
|
||||
*
|
||||
* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along with
|
||||
* this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
|
||||
*
|
||||
*
|
||||
******************************************************************************/
|
||||
#ifndef __HAL_VERSION_DEF_H__
|
||||
#define __HAL_VERSION_DEF_H__
|
||||
|
||||
enum HAL_IC_TYPE {
|
||||
CHIP_8192S = 0,
|
||||
CHIP_8188C = 1,
|
||||
CHIP_8192C = 2,
|
||||
CHIP_8192D = 3,
|
||||
CHIP_8723A = 4,
|
||||
CHIP_8188E = 5,
|
||||
CHIP_8881A = 6,
|
||||
CHIP_8812A = 7,
|
||||
CHIP_8821A = 8,
|
||||
CHIP_8723B = 9,
|
||||
CHIP_8192E = 10,
|
||||
};
|
||||
|
||||
enum HAL_CHIP_TYPE {
|
||||
TEST_CHIP = 0,
|
||||
NORMAL_CHIP = 1,
|
||||
FPGA = 2,
|
||||
};
|
||||
|
||||
enum HAL_CUT_VERSION {
|
||||
A_CUT_VERSION = 0,
|
||||
B_CUT_VERSION = 1,
|
||||
C_CUT_VERSION = 2,
|
||||
D_CUT_VERSION = 3,
|
||||
E_CUT_VERSION = 4,
|
||||
F_CUT_VERSION = 5,
|
||||
G_CUT_VERSION = 6,
|
||||
};
|
||||
|
||||
enum HAL_VENDOR {
|
||||
CHIP_VENDOR_TSMC = 0,
|
||||
CHIP_VENDOR_UMC = 1,
|
||||
};
|
||||
|
||||
enum HAL_RF_TYPE {
|
||||
RF_TYPE_1T1R = 0,
|
||||
RF_TYPE_1T2R = 1,
|
||||
RF_TYPE_2T2R = 2,
|
||||
RF_TYPE_2T3R = 3,
|
||||
RF_TYPE_2T4R = 4,
|
||||
RF_TYPE_3T3R = 5,
|
||||
RF_TYPE_3T4R = 6,
|
||||
RF_TYPE_4T4R = 7,
|
||||
};
|
||||
|
||||
struct HAL_VERSION {
|
||||
enum HAL_IC_TYPE ICType;
|
||||
enum HAL_CHIP_TYPE ChipType;
|
||||
enum HAL_CUT_VERSION CUTVersion;
|
||||
enum HAL_VENDOR VendorType;
|
||||
enum HAL_RF_TYPE RFType;
|
||||
u8 ROMVer;
|
||||
};
|
||||
|
||||
/* Get element */
|
||||
#define GET_CVID_IC_TYPE(version) (((version).ICType))
|
||||
#define GET_CVID_CHIP_TYPE(version) (((version).ChipType))
|
||||
#define GET_CVID_RF_TYPE(version) (((version).RFType))
|
||||
#define GET_CVID_MANUFACTUER(version) (((version).VendorType))
|
||||
#define GET_CVID_CUT_VERSION(version) (((version).CUTVersion))
|
||||
#define GET_CVID_ROM_VERSION(version) (((version).ROMVer) & ROM_VERSION_MASK)
|
||||
|
||||
/* Common Macro. -- */
|
||||
/* HAL_VERSION VersionID */
|
||||
|
||||
/* HAL_IC_TYPE_E */
|
||||
#define IS_81XXC(version) \
|
||||
(((GET_CVID_IC_TYPE(version) == CHIP_8192C) || \
|
||||
(GET_CVID_IC_TYPE(version) == CHIP_8188C)) ? true : false)
|
||||
#define IS_8723_SERIES(version) \
|
||||
((GET_CVID_IC_TYPE(version) == CHIP_8723A) ? true : false)
|
||||
#define IS_92D(version) \
|
||||
((GET_CVID_IC_TYPE(version) == CHIP_8192D) ? true : false)
|
||||
#define IS_8188E(version) \
|
||||
((GET_CVID_IC_TYPE(version) == CHIP_8188E) ? true : false)
|
||||
|
||||
/* HAL_CHIP_TYPE_E */
|
||||
#define IS_TEST_CHIP(version) \
|
||||
((GET_CVID_CHIP_TYPE(version) == TEST_CHIP) ? true : false)
|
||||
#define IS_NORMAL_CHIP(version) \
|
||||
((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? true : false)
|
||||
|
||||
/* HAL_CUT_VERSION_E */
|
||||
#define IS_A_CUT(version) \
|
||||
((GET_CVID_CUT_VERSION(version) == A_CUT_VERSION) ? true : false)
|
||||
#define IS_B_CUT(version) \
|
||||
((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? true : false)
|
||||
#define IS_C_CUT(version) \
|
||||
((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? true : false)
|
||||
#define IS_D_CUT(version) \
|
||||
((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? true : false)
|
||||
#define IS_E_CUT(version) \
|
||||
((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? true : false)
|
||||
|
||||
|
||||
/* HAL_VENDOR_E */
|
||||
#define IS_CHIP_VENDOR_TSMC(version) \
|
||||
((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_TSMC) ? true : false)
|
||||
#define IS_CHIP_VENDOR_UMC(version) \
|
||||
((GET_CVID_MANUFACTUER(version) == CHIP_VENDOR_UMC) ? true : false)
|
||||
|
||||
/* HAL_RF_TYPE_E */
|
||||
#define IS_1T1R(version) \
|
||||
((GET_CVID_RF_TYPE(version) == RF_TYPE_1T1R) ? true : false)
|
||||
#define IS_1T2R(version) \
|
||||
((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R) ? true : false)
|
||||
#define IS_2T2R(version) \
|
||||
((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R) ? true : false)
|
||||
|
||||
/* Chip version Macro. -- */
|
||||
#define IS_81XXC_TEST_CHIP(version) \
|
||||
((IS_81XXC(version) && (!IS_NORMAL_CHIP(version))) ? true : false)
|
||||
|
||||
#define IS_92C_SERIAL(version) \
|
||||
((IS_81XXC(version) && IS_2T2R(version)) ? true : false)
|
||||
#define IS_81xxC_VENDOR_UMC_A_CUT(version) \
|
||||
(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \
|
||||
(IS_A_CUT(version) ? true : false) : false) : false)
|
||||
#define IS_81xxC_VENDOR_UMC_B_CUT(version) \
|
||||
(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \
|
||||
(IS_B_CUT(version) ? true : false) : false) : false)
|
||||
#define IS_81xxC_VENDOR_UMC_C_CUT(version) \
|
||||
(IS_81XXC(version) ? (IS_CHIP_VENDOR_UMC(version) ? \
|
||||
(IS_C_CUT(version) ? true : false) : false) : false)
|
||||
|
||||
#define IS_NORMAL_CHIP92D(version) \
|
||||
((IS_92D(version)) ? \
|
||||
((GET_CVID_CHIP_TYPE(version) == NORMAL_CHIP) ? true : false) : false)
|
||||
|
||||
#define IS_92D_SINGLEPHY(version) \
|
||||
((IS_92D(version)) ? (IS_2T2R(version) ? true : false) : false)
|
||||
#define IS_92D_C_CUT(version) \
|
||||
((IS_92D(version)) ? (IS_C_CUT(version) ? true : false) : false)
|
||||
#define IS_92D_D_CUT(version) \
|
||||
((IS_92D(version)) ? (IS_D_CUT(version) ? true : false) : false)
|
||||
#define IS_92D_E_CUT(version) \
|
||||
((IS_92D(version)) ? (IS_E_CUT(version) ? true : false) : false)
|
||||
|
||||
#define IS_8723A_A_CUT(version) \
|
||||
((IS_8723_SERIES(version)) ? (IS_A_CUT(version) ? true : false) : false)
|
||||
#define IS_8723A_B_CUT(version) \
|
||||
((IS_8723_SERIES(version)) ? (IS_B_CUT(version) ? true : false) : false)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user