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MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6
MIPS R6 removed quite a few R2 instructions. However, there is plenty of <R6 userland code so we add an in-kernel emulator so we can still be able to execute all R2 userland out there. The emulator comes with a handy debugfs under /mips/ directory (r2-emul-stats) to provide some basic statistics of the instructions that are being emulated. Below are some statistics from booting a minimal buildroot image: Instruction Total BDslot ------------------------------ movs 236969 0 hilo 56686 0 muls 55279 0 divs 10941 0 dsps 0 0 bops 1 0 traps 0 0 fpus 0 0 loads 214981 17 stores 103364 0 llsc 56898 0 dsemul 150418 0 jr 370158 bltzl 43 bgezl 1594 bltzll 0 bgezll 0 bltzal 39 bgezal 39 beql 14503 bnel 138741 blezl 0 bgtzl 3988 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
This commit is contained in:
Leonid Yegoshin
Markos Chandras
parent
b55b9e2715
commit
b0a668fb20
@ -2063,6 +2063,19 @@ config MIPS_MT_FPAFF
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default y
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depends on MIPS_MT_SMP
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config MIPSR2_TO_R6_EMULATOR
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bool "MIPS R2-to-R6 emulator"
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depends on CPU_MIPSR6 && !SMP
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default y
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help
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Choose this option if you want to run non-R6 MIPS userland code.
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Even if you say 'Y' here, the emulator will still be disabled by
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default. You can enable it using the 'mipsr2emul' kernel option.
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The only reason this is a build-time option is to save ~14K from the
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final kernel image.
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comment "MIPS R2-to-R6 emulator is only available for UP kernels"
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depends on SMP && CPU_MIPSR6
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config MIPS_VPE_LOADER
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bool "VPE loader support."
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depends on SYS_SUPPORTS_MULTITHREADING && MODULES
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@ -13,9 +13,6 @@
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#include <asm/ptrace.h>
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#include <asm/inst.h>
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static int mipsr2_emulation = 0;
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#define NO_R6EMU (cpu_has_mips_r6 && !mipsr2_emulation)
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extern int __isa_exception_epc(struct pt_regs *regs);
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extern int __compute_return_epc(struct pt_regs *regs);
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extern int __compute_return_epc_for_insn(struct pt_regs *regs,
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96
arch/mips/include/asm/mips-r2-to-r6-emul.h
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96
arch/mips/include/asm/mips-r2-to-r6-emul.h
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@ -0,0 +1,96 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 2014 Imagination Technologies Ltd.
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* Author: Markos Chandras <markos.chandras@imgtec.com>
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*/
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#ifndef __ASM_MIPS_R2_TO_R6_EMUL_H
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#define __ASM_MIPS_R2_TO_R6_EMUL_H
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struct mips_r2_emulator_stats {
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u64 movs;
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u64 hilo;
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u64 muls;
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u64 divs;
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u64 dsps;
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u64 bops;
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u64 traps;
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u64 fpus;
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u64 loads;
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u64 stores;
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u64 llsc;
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u64 dsemul;
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};
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struct mips_r2br_emulator_stats {
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u64 jrs;
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u64 bltzl;
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u64 bgezl;
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u64 bltzll;
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u64 bgezll;
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u64 bltzall;
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u64 bgezall;
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u64 bltzal;
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u64 bgezal;
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u64 beql;
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u64 bnel;
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u64 blezl;
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u64 bgtzl;
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};
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#ifdef CONFIG_DEBUG_FS
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#define MIPS_R2_STATS(M) \
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do { \
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u32 nir; \
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int err; \
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\
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preempt_disable(); \
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__this_cpu_inc(mipsr2emustats.M); \
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err = __get_user(nir, (u32 __user *)regs->cp0_epc); \
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if (!err) { \
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if (nir == BREAK_MATH) \
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__this_cpu_inc(mipsr2bdemustats.M); \
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} \
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preempt_enable(); \
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} while (0)
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#define MIPS_R2BR_STATS(M) \
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do { \
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preempt_disable(); \
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__this_cpu_inc(mipsr2bremustats.M); \
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preempt_enable(); \
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} while (0)
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#else
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#define MIPS_R2_STATS(M) do { } while (0)
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#define MIPS_R2BR_STATS(M) do { } while (0)
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#endif /* CONFIG_DEBUG_FS */
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struct r2_decoder_table {
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u32 mask;
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u32 code;
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int (*func)(struct pt_regs *regs, u32 inst);
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};
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extern void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
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const char *str);
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#ifndef CONFIG_MIPSR2_TO_R6_EMULATOR
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static int mipsr2_emulation;
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static __maybe_unused int mipsr2_decoder(struct pt_regs *regs, u32 inst) { return 0; };
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#else
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/* MIPS R2 Emulator ON/OFF */
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extern int mipsr2_emulation;
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extern int mipsr2_decoder(struct pt_regs *regs, u32 inst);
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#endif /* CONFIG_MIPSR2_TO_R6_EMULATOR */
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#define NO_R6EMU (cpu_has_mips_r6 && !mipsr2_emulation)
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#endif /* __ASM_MIPS_R2_TO_R6_EMUL_H */
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@ -90,6 +90,7 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o
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obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o
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obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o
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obj-$(CONFIG_MIPSR2_TO_R6_EMULATOR) += mips-r2-to-r6-emul.o
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CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -x c /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
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@ -16,6 +16,7 @@
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#include <asm/fpu.h>
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#include <asm/fpu_emulator.h>
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#include <asm/inst.h>
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#include <asm/mips-r2-to-r6-emul.h>
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#include <asm/ptrace.h>
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#include <asm/uaccess.h>
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2378
arch/mips/kernel/mips-r2-to-r6-emul.c
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2378
arch/mips/kernel/mips-r2-to-r6-emul.c
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File diff suppressed because it is too large
Load Diff
@ -46,6 +46,7 @@
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#include <asm/fpu.h>
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#include <asm/fpu_emulator.h>
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#include <asm/idle.h>
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#include <asm/mips-r2-to-r6-emul.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/module.h>
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@ -837,7 +838,7 @@ out:
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exception_exit(prev_state);
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}
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static void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
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void do_trap_or_bp(struct pt_regs *regs, unsigned int code,
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const char *str)
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{
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siginfo_t info;
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@ -1027,7 +1028,32 @@ asmlinkage void do_ri(struct pt_regs *regs)
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unsigned int opcode = 0;
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int status = -1;
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/*
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* Avoid any kernel code. Just emulate the R2 instruction
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* as quickly as possible.
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*/
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if (mipsr2_emulation && cpu_has_mips_r6 &&
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likely(user_mode(regs))) {
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if (likely(get_user(opcode, epc) >= 0)) {
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status = mipsr2_decoder(regs, opcode);
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switch (status) {
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case 0:
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case SIGEMT:
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return;
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case SIGILL:
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goto no_r2_instr;
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default:
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process_fpemu_return(status,
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¤t->thread.cp0_baduaddr);
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return;
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}
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}
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}
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no_r2_instr:
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prev_state = exception_enter();
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if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs),
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SIGILL) == NOTIFY_STOP)
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goto out;
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@ -48,6 +48,7 @@
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#include <asm/processor.h>
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#include <asm/fpu_emulator.h>
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#include <asm/fpu.h>
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#include <asm/mips-r2-to-r6-emul.h>
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#include "ieee754.h"
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@ -68,7 +69,7 @@ static int fpux_emu(struct pt_regs *,
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#define modeindex(v) ((v) & FPU_CSR_RM)
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/* convert condition code register number to csr bit */
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static const unsigned int fpucondbit[8] = {
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const unsigned int fpucondbit[8] = {
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FPU_CSR_COND0,
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FPU_CSR_COND1,
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FPU_CSR_COND2,
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