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Merge branch 'remotes/lorenzo/pci/power-slot'
- Add of_pci_get_slot_power_limit() to parse the 'slot-power-limit-milliwatt' DT property (Pali Rohár) - Add mvebu support for sending Set_Slot_Power_Limit message (Pali Rohár) * remotes/lorenzo/pci/power-slot: PCI: mvebu: Add support for sending Set_Slot_Power_Limit message PCI: Add function for parsing 'slot-power-limit-milliwatt' DT property PCI: Add PCI_EXP_SLTCTL_ASPL_DISABLE macro
This commit is contained in:
Bjorn Helgaas
commit
b0266c4289
@ -8,6 +8,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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@ -66,6 +67,12 @@
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#define PCIE_STAT_BUS 0xff00
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#define PCIE_STAT_DEV 0x1f0000
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#define PCIE_STAT_LINK_DOWN BIT(0)
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#define PCIE_SSPL_OFF 0x1a0c
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#define PCIE_SSPL_VALUE_SHIFT 0
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#define PCIE_SSPL_VALUE_MASK GENMASK(7, 0)
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#define PCIE_SSPL_SCALE_SHIFT 8
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#define PCIE_SSPL_SCALE_MASK GENMASK(9, 8)
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#define PCIE_SSPL_ENABLE BIT(16)
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#define PCIE_RC_RTSTA 0x1a14
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#define PCIE_DEBUG_CTRL 0x1a60
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#define PCIE_DEBUG_SOFT_RESET BIT(20)
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@ -111,6 +118,8 @@ struct mvebu_pcie_port {
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struct mvebu_pcie_window iowin;
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u32 saved_pcie_stat;
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struct resource regs;
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u8 slot_power_limit_value;
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u8 slot_power_limit_scale;
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struct irq_domain *intx_irq_domain;
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raw_spinlock_t irq_lock;
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int intx_irq;
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@ -239,7 +248,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
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static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
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{
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u32 ctrl, lnkcap, cmd, dev_rev, unmask;
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u32 ctrl, lnkcap, cmd, dev_rev, unmask, sspl;
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/* Setup PCIe controller to Root Complex mode. */
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ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
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@ -292,6 +301,20 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
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/* Point PCIe unit MBUS decode windows to DRAM space. */
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mvebu_pcie_setup_wins(port);
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/*
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* Program Root Port to automatically send Set_Slot_Power_Limit
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* PCIe Message when changing status from Dl_Down to Dl_Up and valid
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* slot power limit was specified.
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*/
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sspl = mvebu_readl(port, PCIE_SSPL_OFF);
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sspl &= ~(PCIE_SSPL_VALUE_MASK | PCIE_SSPL_SCALE_MASK | PCIE_SSPL_ENABLE);
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if (port->slot_power_limit_value) {
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sspl |= port->slot_power_limit_value << PCIE_SSPL_VALUE_SHIFT;
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sspl |= port->slot_power_limit_scale << PCIE_SSPL_SCALE_SHIFT;
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sspl |= PCIE_SSPL_ENABLE;
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}
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mvebu_writel(port, sspl, PCIE_SSPL_OFF);
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/* Mask all interrupt sources. */
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mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
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@ -628,9 +651,24 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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(PCI_EXP_LNKSTA_DLLLA << 16) : 0);
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break;
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case PCI_EXP_SLTCTL:
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*value = PCI_EXP_SLTSTA_PDS << 16;
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case PCI_EXP_SLTCTL: {
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u16 slotctl = le16_to_cpu(bridge->pcie_conf.slotctl);
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u16 slotsta = le16_to_cpu(bridge->pcie_conf.slotsta);
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u32 val = 0;
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/*
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* When slot power limit was not specified in DT then
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* ASPL_DISABLE bit is stored only in emulated config space.
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* Otherwise reflect status of PCIE_SSPL_ENABLE bit in HW.
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*/
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if (!port->slot_power_limit_value)
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val |= slotctl & PCI_EXP_SLTCTL_ASPL_DISABLE;
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else if (!(mvebu_readl(port, PCIE_SSPL_OFF) & PCIE_SSPL_ENABLE))
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val |= PCI_EXP_SLTCTL_ASPL_DISABLE;
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/* This callback is 32-bit and in high bits is slot status. */
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val |= slotsta << 16;
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*value = val;
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break;
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}
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case PCI_EXP_RTSTA:
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*value = mvebu_readl(port, PCIE_RC_RTSTA);
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@ -774,6 +812,22 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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mvebu_writel(port, new, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
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break;
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case PCI_EXP_SLTCTL:
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/*
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* Allow to change PCIE_SSPL_ENABLE bit only when slot power
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* limit was specified in DT and configured into HW.
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*/
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if ((mask & PCI_EXP_SLTCTL_ASPL_DISABLE) &&
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port->slot_power_limit_value) {
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u32 sspl = mvebu_readl(port, PCIE_SSPL_OFF);
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if (new & PCI_EXP_SLTCTL_ASPL_DISABLE)
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sspl &= ~PCIE_SSPL_ENABLE;
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else
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sspl |= PCIE_SSPL_ENABLE;
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mvebu_writel(port, sspl, PCIE_SSPL_OFF);
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}
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break;
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case PCI_EXP_RTSTA:
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/*
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* PME Status bit in Root Status Register (PCIE_RC_RTSTA)
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@ -868,8 +922,26 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
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/*
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* Older mvebu hardware provides PCIe Capability structure only in
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* version 1. New hardware provides it in version 2.
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* Enable slot support which is emulated.
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*/
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bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver);
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bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver | PCI_EXP_FLAGS_SLOT);
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/*
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* Set Presence Detect State bit permanently as there is no support for
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* unplugging PCIe card from the slot. Assume that PCIe card is always
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* connected in slot.
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*
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* Set physical slot number to port+1 as mvebu ports are indexed from
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* zero and zero value is reserved for ports within the same silicon
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* as Root Port which is not mvebu case.
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*
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* Also set correct slot power limit.
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*/
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bridge->pcie_conf.slotcap = cpu_to_le32(
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FIELD_PREP(PCI_EXP_SLTCAP_SPLV, port->slot_power_limit_value) |
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FIELD_PREP(PCI_EXP_SLTCAP_SPLS, port->slot_power_limit_scale) |
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FIELD_PREP(PCI_EXP_SLTCAP_PSN, port->port+1));
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bridge->pcie_conf.slotsta = cpu_to_le16(PCI_EXP_SLTSTA_PDS);
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bridge->subsystem_vendor_id = ssdev_id & 0xffff;
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bridge->subsystem_id = ssdev_id >> 16;
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@ -1191,6 +1263,7 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
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{
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struct device *dev = &pcie->pdev->dev;
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enum of_gpio_flags flags;
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u32 slot_power_limit;
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int reset_gpio, ret;
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u32 num_lanes;
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@ -1291,6 +1364,15 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
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port->reset_gpio = gpio_to_desc(reset_gpio);
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}
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slot_power_limit = of_pci_get_slot_power_limit(child,
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&port->slot_power_limit_value,
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&port->slot_power_limit_scale);
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if (slot_power_limit)
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dev_info(dev, "%s: Slot power limit %u.%uW\n",
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port->name,
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slot_power_limit / 1000,
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(slot_power_limit / 100) % 10);
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port->clk = of_clk_get_by_name(child, NULL);
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if (IS_ERR(port->clk)) {
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dev_err(dev, "%s: cannot get clock\n", port->name);
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@ -1588,7 +1670,7 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
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{
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struct mvebu_pcie *pcie = platform_get_drvdata(pdev);
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struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
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u32 cmd;
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u32 cmd, sspl;
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int i;
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/* Remove PCI bus with all devices. */
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@ -1625,6 +1707,11 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
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/* Free config space for emulated root bridge. */
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pci_bridge_emul_cleanup(&port->bridge);
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/* Disable sending Set_Slot_Power_Limit PCIe Message. */
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sspl = mvebu_readl(port, PCIE_SSPL_OFF);
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sspl &= ~(PCIE_SSPL_VALUE_MASK | PCIE_SSPL_SCALE_MASK | PCIE_SSPL_ENABLE);
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mvebu_writel(port, sspl, PCIE_SSPL_OFF);
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/* Disable and clear BARs and windows. */
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mvebu_pcie_disable_wins(port);
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@ -633,3 +633,73 @@ int of_pci_get_max_link_speed(struct device_node *node)
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return max_link_speed;
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}
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EXPORT_SYMBOL_GPL(of_pci_get_max_link_speed);
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/**
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* of_pci_get_slot_power_limit - Parses the "slot-power-limit-milliwatt"
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* property.
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*
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* @node: device tree node with the slot power limit information
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* @slot_power_limit_value: pointer where the value should be stored in PCIe
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* Slot Capabilities Register format
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* @slot_power_limit_scale: pointer where the scale should be stored in PCIe
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* Slot Capabilities Register format
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*
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* Returns the slot power limit in milliwatts and if @slot_power_limit_value
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* and @slot_power_limit_scale pointers are non-NULL, fills in the value and
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* scale in format used by PCIe Slot Capabilities Register.
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*
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* If the property is not found or is invalid, returns 0.
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*/
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u32 of_pci_get_slot_power_limit(struct device_node *node,
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u8 *slot_power_limit_value,
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u8 *slot_power_limit_scale)
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{
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u32 slot_power_limit_mw;
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u8 value, scale;
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if (of_property_read_u32(node, "slot-power-limit-milliwatt",
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&slot_power_limit_mw))
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slot_power_limit_mw = 0;
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/* Calculate Slot Power Limit Value and Slot Power Limit Scale */
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if (slot_power_limit_mw == 0) {
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value = 0x00;
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scale = 0;
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} else if (slot_power_limit_mw <= 255) {
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value = slot_power_limit_mw;
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scale = 3;
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} else if (slot_power_limit_mw <= 255*10) {
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value = slot_power_limit_mw / 10;
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scale = 2;
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slot_power_limit_mw = slot_power_limit_mw / 10 * 10;
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} else if (slot_power_limit_mw <= 255*100) {
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value = slot_power_limit_mw / 100;
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scale = 1;
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slot_power_limit_mw = slot_power_limit_mw / 100 * 100;
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} else if (slot_power_limit_mw <= 239*1000) {
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value = slot_power_limit_mw / 1000;
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scale = 0;
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slot_power_limit_mw = slot_power_limit_mw / 1000 * 1000;
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} else if (slot_power_limit_mw < 250*1000) {
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value = 0xEF;
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scale = 0;
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slot_power_limit_mw = 239*1000;
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} else if (slot_power_limit_mw <= 600*1000) {
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value = 0xF0 + (slot_power_limit_mw / 1000 - 250) / 25;
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scale = 0;
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slot_power_limit_mw = slot_power_limit_mw / (1000*25) * (1000*25);
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} else {
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value = 0xFE;
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scale = 0;
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slot_power_limit_mw = 600*1000;
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}
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if (slot_power_limit_value)
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*slot_power_limit_value = value;
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if (slot_power_limit_scale)
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*slot_power_limit_scale = scale;
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return slot_power_limit_mw;
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}
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EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit);
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@ -627,6 +627,9 @@ struct device_node;
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int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
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int of_get_pci_domain_nr(struct device_node *node);
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int of_pci_get_max_link_speed(struct device_node *node);
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u32 of_pci_get_slot_power_limit(struct device_node *node,
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u8 *slot_power_limit_value,
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u8 *slot_power_limit_scale);
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void pci_set_of_node(struct pci_dev *dev);
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void pci_release_of_node(struct pci_dev *dev);
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void pci_set_bus_of_node(struct pci_bus *bus);
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@ -653,6 +656,18 @@ of_pci_get_max_link_speed(struct device_node *node)
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return -EINVAL;
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}
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static inline u32
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of_pci_get_slot_power_limit(struct device_node *node,
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u8 *slot_power_limit_value,
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u8 *slot_power_limit_scale)
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{
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if (slot_power_limit_value)
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*slot_power_limit_value = 0;
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if (slot_power_limit_scale)
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*slot_power_limit_scale = 0;
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return 0;
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}
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static inline void pci_set_of_node(struct pci_dev *dev) { }
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static inline void pci_release_of_node(struct pci_dev *dev) { }
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static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
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@ -616,6 +616,7 @@
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#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */
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#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
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#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
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#define PCI_EXP_SLTCTL_ASPL_DISABLE 0x2000 /* Auto Slot Power Limit Disable */
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#define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
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#define PCI_EXP_SLTSTA 0x1a /* Slot Status */
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#define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */
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