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staging: rtl8723au: phy_SsPwrSwitch92CU() was never called with bRegSSPwrLvl != 1
Get rid of the alternate code paths since these weren't used and have never been tested according to the in-code comments. Signed-off-by: Jes Sorensen <Jes.Sorensen@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jes Sorensen
Greg Kroah-Hartman
parent
0e316c2251
commit
b024793188
@ -26,8 +26,7 @@
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#include <usb_ops.h>
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static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
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enum rt_rf_power_state eRFPowerState,
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int bRegSSPwrLvl);
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enum rt_rf_power_state eRFPowerState);
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static void
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_ConfigChipOutEP(struct rtw_adapter *pAdapter, u8 NumOutPipe)
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@ -513,9 +512,7 @@ int rtl8723au_hal_init(struct rtw_adapter *Adapter)
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Adapter->hw_init_completed = false;
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if (Adapter->pwrctrlpriv.bkeepfwalive) {
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/* here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2
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needs to be verified */
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phy_SsPwrSwitch92CU(Adapter, rf_on, 1);
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phy_SsPwrSwitch92CU(Adapter, rf_on);
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if (pHalData->bIQKInitialized) {
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rtl8723a_phy_iq_calibrate(Adapter, true);
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@ -776,112 +773,50 @@ exit:
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}
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static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
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enum rt_rf_power_state eRFPowerState,
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int bRegSSPwrLvl)
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enum rt_rf_power_state eRFPowerState)
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{
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struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
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u8 value8, sps0;
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u8 bytetmp;
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u8 sps0;
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sps0 = rtl8723au_read8(Adapter, REG_SPS0_CTRL);
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switch (eRFPowerState) {
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case rf_on:
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if (bRegSSPwrLvl == 1) {
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/* 1. Enable MAC Clock. Can not be enabled now. */
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/* WriteXBYTE(REG_SYS_CLKR+1,
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ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */
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/* 1. Enable MAC Clock. Can not be enabled now. */
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/* WriteXBYTE(REG_SYS_CLKR+1,
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ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); */
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/* 2. Force PWM, Enable SPS18_LDO_Marco_Block */
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rtl8723au_write8(Adapter, REG_SPS0_CTRL,
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sps0 | BIT(0) | BIT(3));
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/* 2. Force PWM, Enable SPS18_LDO_Marco_Block */
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rtl8723au_write8(Adapter, REG_SPS0_CTRL,
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sps0 | BIT(0) | BIT(3));
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/* 3. restore BB, AFE control register. */
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/* RF */
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x380038, 1);
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else
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x38, 1);
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PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
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PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0);
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/* 3. restore BB, AFE control register. */
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/* RF */
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x380038, 1);
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else
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x38, 1);
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PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
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PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0);
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/* AFE */
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x63DB25A0);
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else if (pHalData->rf_type == RF_1T1R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x631B25A0);
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/* AFE */
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x63DB25A0);
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else if (pHalData->rf_type == RF_1T1R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x631B25A0);
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/* 4. issue 3-wire command that RF set to Rx idle
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mode. This is used to re-write the RX idle mode. */
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/* We can only prvide a usual value instead and then
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HW will modify the value by itself. */
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PHY_SetRFReg(Adapter, RF_PATH_A, 0,
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/* 4. issue 3-wire command that RF set to Rx idle
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mode. This is used to re-write the RX idle mode. */
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/* We can only prvide a usual value instead and then
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HW will modify the value by itself. */
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PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0x32D95);
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if (pHalData->rf_type == RF_2T2R) {
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PHY_SetRFReg(Adapter, RF_PATH_B, 0,
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bRFRegOffsetMask, 0x32D95);
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if (pHalData->rf_type == RF_2T2R) {
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PHY_SetRFReg(Adapter, RF_PATH_B, 0,
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bRFRegOffsetMask, 0x32D95);
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}
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} else { /* Level 2 or others. */
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/* h. AFE_PLL_CTRL 0x28[7:0] = 0x80
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disable AFE PLL */
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rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x81);
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/* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F
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gated AFE DIG_CLOCK */
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rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0x800F);
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mdelay(1);
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/* 2. Force PWM, Enable SPS18_LDO_Marco_Block */
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rtl8723au_write8(Adapter, REG_SPS0_CTRL,
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sps0 | BIT(0) | BIT(3));
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/* 3. restore BB, AFE control register. */
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/* RF */
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x380038, 1);
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else
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x38, 1);
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PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1);
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PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 0);
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/* AFE */
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA,
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bMaskDWord, 0x63DB25A0);
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else if (pHalData->rf_type == RF_1T1R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA,
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bMaskDWord, 0x631B25A0);
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/* 4. issue 3-wire command that RF set to Rx idle
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mode. This is used to re-write the RX idle mode. */
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/* We can only prvide a usual value instead and
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then HW will modify the value by itself. */
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PHY_SetRFReg(Adapter, RF_PATH_A, 0,
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bRFRegOffsetMask, 0x32D95);
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if (pHalData->rf_type == RF_2T2R) {
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PHY_SetRFReg(Adapter, RF_PATH_B, 0,
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bRFRegOffsetMask, 0x32D95);
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}
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/* 5. gated MAC Clock */
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bytetmp = rtl8723au_read8(Adapter, REG_APSD_CTRL);
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rtl8723au_write8(Adapter, REG_APSD_CTRL,
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bytetmp & ~BIT(6));
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mdelay(10);
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/* Set BB reset at first */
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/* 0x16 */
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rtl8723au_write8(Adapter, REG_SYS_FUNC_EN, 0x17);
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/* Enable TX */
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rtl8723au_write8(Adapter, REG_TXPAUSE, 0x0);
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}
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break;
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case rf_sleep:
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@ -890,146 +825,57 @@ static void phy_SsPwrSwitch92CU(struct rtw_adapter *Adapter,
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sps0 &= ~BIT(0);
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else
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sps0 &= ~(BIT(0) | BIT(3));
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if (bRegSSPwrLvl == 1) {
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RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
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/* Disable RF and BB only for SelectSuspend. */
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/* 1. Set BB/RF to shutdown. */
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/* (1) Reg878[5:3]= 0 RF rx_code for
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preamble power saving */
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/* (2)Reg878[21:19]= 0 Turn off RF-B */
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/* (3) RegC04[7:4]= 0 Turn off all paths
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for packet detection */
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/* (4) Reg800[1] = 1 enable preamble power
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saving */
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
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PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
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bMaskDWord);
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
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PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
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bMaskDWord);
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
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PHY_QueryBBReg(Adapter, rFPGA0_RFMOD,
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bMaskDWord);
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if (pHalData->rf_type == RF_2T2R) {
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x380038, 0);
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} else if (pHalData->rf_type == RF_1T1R) {
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x38, 0);
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}
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PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
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PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
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RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL1\n"));
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/* Disable RF and BB only for SelectSuspend. */
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/* 2 .AFE control register to power down. bit[30:22] */
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
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PHY_QueryBBReg(Adapter, rRx_Wait_CCA,
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bMaskDWord);
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x00DB25A0);
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else if (pHalData->rf_type == RF_1T1R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x001B25A0);
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/* 3. issue 3-wire command that RF set to power down.*/
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PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetRFReg(Adapter, RF_PATH_B, 0,
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bRFRegOffsetMask, 0);
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/* 4. Force PFM , disable SPS18_LDO_Marco_Block */
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rtl8723au_write8(Adapter, REG_SPS0_CTRL, sps0);
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} else { /* Level 2 or others. */
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RT_TRACE(_module_hal_init_c_, _drv_err_, ("SS LVL2\n"));
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{
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u8 eRFPath = RF_PATH_A, value8 = 0;
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rtl8723au_write8(Adapter, REG_TXPAUSE, 0xFF);
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PHY_SetRFReg(Adapter,
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(enum RF_RADIO_PATH)eRFPath,
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0x0, bMaskByte0, 0x0);
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value8 |= APSDOFF;
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/* 0x40 */
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rtl8723au_write8(Adapter, REG_APSD_CTRL,
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value8);
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/* After switch APSD, we need to delay
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for stability */
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mdelay(10);
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/* Set BB reset at first */
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value8 = 0;
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value8 |= (FEN_USBD | FEN_USBA |
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FEN_BB_GLB_RSTn);
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/* 0x16 */
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rtl8723au_write8(Adapter, REG_SYS_FUNC_EN,
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value8);
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}
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/* Disable RF and BB only for SelectSuspend. */
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/* 1. Set BB/RF to shutdown. */
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/* (1) Reg878[5:3]= 0 RF rx_code for
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preamble power saving */
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/* (2)Reg878[21:19]= 0 Turn off RF-B */
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/* (3) RegC04[7:4]= 0 Turn off all paths for
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packet detection */
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/* (4) Reg800[1] = 1 enable preamble power
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saving */
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
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PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
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bMaskDWord);
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
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PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
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bMaskDWord);
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
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PHY_QueryBBReg(Adapter, rFPGA0_RFMOD,
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bMaskDWord);
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x380038, 0);
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else if (pHalData->rf_type == RF_1T1R)
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x38, 0);
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PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
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PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
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/* 2 .AFE control register to power down. bit[30:22] */
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
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PHY_QueryBBReg(Adapter, rRx_Wait_CCA,
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bMaskDWord);
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x00DB25A0);
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else if (pHalData->rf_type == RF_1T1R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x001B25A0);
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/* 3. issue 3-wire command that RF set to power down. */
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PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetRFReg(Adapter, RF_PATH_B, 0,
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bRFRegOffsetMask, 0);
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/* 4. Force PFM , disable SPS18_LDO_Marco_Block */
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rtl8723au_write8(Adapter, REG_SPS0_CTRL, sps0);
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/* 2010/10/13 MH/Isaachsu exchange sequence. */
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/* h. AFE_PLL_CTRL 0x28[7:0] = 0x80
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disable AFE PLL */
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rtl8723au_write8(Adapter, REG_AFE_PLL_CTRL, 0x80);
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mdelay(1);
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/* i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F
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gated AFE DIG_CLOCK */
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rtl8723au_write16(Adapter, REG_AFE_XTAL_CTRL, 0xA80F);
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/* 1. Set BB/RF to shutdown. */
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/* (1) Reg878[5:3]= 0 RF rx_code for
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preamble power saving */
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/* (2)Reg878[21:19]= 0 Turn off RF-B */
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/* (3) RegC04[7:4]= 0 Turn off all paths
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for packet detection */
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/* (4) Reg800[1] = 1 enable preamble power saving */
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] =
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PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter,
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bMaskDWord);
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] =
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PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable,
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bMaskDWord);
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] =
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PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord);
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if (pHalData->rf_type == RF_2T2R) {
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter,
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0x380038, 0);
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} else if (pHalData->rf_type == RF_1T1R) {
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PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0);
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}
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PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0);
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PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT(1), 1);
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/* 2 .AFE control register to power down. bit[30:22] */
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Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] =
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PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord);
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x00DB25A0);
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else if (pHalData->rf_type == RF_1T1R)
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PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord,
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0x001B25A0);
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/* 3. issue 3-wire command that RF set to power down.*/
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PHY_SetRFReg(Adapter, RF_PATH_A, 0, bRFRegOffsetMask, 0);
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if (pHalData->rf_type == RF_2T2R)
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PHY_SetRFReg(Adapter, RF_PATH_B, 0,
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bRFRegOffsetMask, 0);
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/* 4. Force PFM , disable SPS18_LDO_Marco_Block */
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rtl8723au_write8(Adapter, REG_SPS0_CTRL, sps0);
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break;
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default:
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break;
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}
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} /* phy_PowerSwitch92CU */
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}
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static void CardDisableRTL8723U(struct rtw_adapter *Adapter)
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{
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