mirror of
https://github.com/torvalds/linux.git
synced 2024-11-07 04:32:03 +00:00
linux-can-fixes-for-3.17-20140918
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iEYEABECAAYFAlQaozkACgkQjTAFq1RaXHMfqQCfYwrXHrzRmTq+/2oohauS1orp 4B8AnRagBwGjDLUKzSBuTM021BMe2D4+ =b1sn -----END PGP SIGNATURE----- Merge tag 'linux-can-fixes-for-3.17-20140918' of git://gitorious.org/linux-can/linux-can Marc Kleine-Budde says: ==================== pull-request: can 2014-09-18 this is a pull request of 8 patches for current net. A patch by Roger Quadros for the c_can driver fixes the swapped parameters of the c_can_hw_raminit_ti() function. Oliver Hartkopp adds the missing PCI ids to the peak_pci driver to support the single channel PCAN ExpressCard 34 adapter. David Dueck converts the at91_can driver to use proper clock handling functions. Then there are 5 patches by David Jander and me which fix several mailbox related problems in the flexcan driver. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
afbe7af1b2
@ -1123,7 +1123,9 @@ static int at91_open(struct net_device *dev)
|
||||
struct at91_priv *priv = netdev_priv(dev);
|
||||
int err;
|
||||
|
||||
clk_enable(priv->clk);
|
||||
err = clk_prepare_enable(priv->clk);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* check or determine and set bittime */
|
||||
err = open_candev(dev);
|
||||
@ -1149,7 +1151,7 @@ static int at91_open(struct net_device *dev)
|
||||
out_close:
|
||||
close_candev(dev);
|
||||
out:
|
||||
clk_disable(priv->clk);
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
return err;
|
||||
}
|
||||
@ -1166,7 +1168,7 @@ static int at91_close(struct net_device *dev)
|
||||
at91_chip_stop(dev, CAN_STATE_STOPPED);
|
||||
|
||||
free_irq(dev->irq, dev);
|
||||
clk_disable(priv->clk);
|
||||
clk_disable_unprepare(priv->clk);
|
||||
|
||||
close_candev(dev);
|
||||
|
||||
|
@ -97,14 +97,14 @@ static void c_can_hw_raminit_ti(const struct c_can_priv *priv, bool enable)
|
||||
ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
|
||||
writel(ctrl, priv->raminit_ctrlreg);
|
||||
ctrl &= ~CAN_RAMINIT_DONE_MASK(priv->instance);
|
||||
c_can_hw_raminit_wait_ti(priv, ctrl, mask);
|
||||
c_can_hw_raminit_wait_ti(priv, mask, ctrl);
|
||||
|
||||
if (enable) {
|
||||
/* Set start bit and wait for the done bit. */
|
||||
ctrl |= CAN_RAMINIT_START_MASK(priv->instance);
|
||||
writel(ctrl, priv->raminit_ctrlreg);
|
||||
ctrl |= CAN_RAMINIT_DONE_MASK(priv->instance);
|
||||
c_can_hw_raminit_wait_ti(priv, ctrl, mask);
|
||||
c_can_hw_raminit_wait_ti(priv, mask, ctrl);
|
||||
}
|
||||
spin_unlock(&raminit_lock);
|
||||
}
|
||||
|
@ -62,7 +62,7 @@
|
||||
#define FLEXCAN_MCR_BCC BIT(16)
|
||||
#define FLEXCAN_MCR_LPRIO_EN BIT(13)
|
||||
#define FLEXCAN_MCR_AEN BIT(12)
|
||||
#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
|
||||
#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x7f)
|
||||
#define FLEXCAN_MCR_IDAM_A (0 << 8)
|
||||
#define FLEXCAN_MCR_IDAM_B (1 << 8)
|
||||
#define FLEXCAN_MCR_IDAM_C (2 << 8)
|
||||
@ -125,7 +125,9 @@
|
||||
FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT)
|
||||
|
||||
/* FLEXCAN interrupt flag register (IFLAG) bits */
|
||||
#define FLEXCAN_TX_BUF_ID 8
|
||||
/* Errata ERR005829 step7: Reserve first valid MB */
|
||||
#define FLEXCAN_TX_BUF_RESERVED 8
|
||||
#define FLEXCAN_TX_BUF_ID 9
|
||||
#define FLEXCAN_IFLAG_BUF(x) BIT(x)
|
||||
#define FLEXCAN_IFLAG_RX_FIFO_OVERFLOW BIT(7)
|
||||
#define FLEXCAN_IFLAG_RX_FIFO_WARN BIT(6)
|
||||
@ -136,6 +138,17 @@
|
||||
|
||||
/* FLEXCAN message buffers */
|
||||
#define FLEXCAN_MB_CNT_CODE(x) (((x) & 0xf) << 24)
|
||||
#define FLEXCAN_MB_CODE_RX_INACTIVE (0x0 << 24)
|
||||
#define FLEXCAN_MB_CODE_RX_EMPTY (0x4 << 24)
|
||||
#define FLEXCAN_MB_CODE_RX_FULL (0x2 << 24)
|
||||
#define FLEXCAN_MB_CODE_RX_OVERRRUN (0x6 << 24)
|
||||
#define FLEXCAN_MB_CODE_RX_RANSWER (0xa << 24)
|
||||
|
||||
#define FLEXCAN_MB_CODE_TX_INACTIVE (0x8 << 24)
|
||||
#define FLEXCAN_MB_CODE_TX_ABORT (0x9 << 24)
|
||||
#define FLEXCAN_MB_CODE_TX_DATA (0xc << 24)
|
||||
#define FLEXCAN_MB_CODE_TX_TANSWER (0xe << 24)
|
||||
|
||||
#define FLEXCAN_MB_CNT_SRR BIT(22)
|
||||
#define FLEXCAN_MB_CNT_IDE BIT(21)
|
||||
#define FLEXCAN_MB_CNT_RTR BIT(20)
|
||||
@ -428,6 +441,14 @@ static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
|
||||
flexcan_write(can_id, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_id);
|
||||
flexcan_write(ctrl, ®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
|
||||
|
||||
/* Errata ERR005829 step8:
|
||||
* Write twice INACTIVE(0x8) code to first MB.
|
||||
*/
|
||||
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
|
||||
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
|
||||
|
||||
return NETDEV_TX_OK;
|
||||
}
|
||||
|
||||
@ -744,6 +765,9 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id)
|
||||
stats->tx_bytes += can_get_echo_skb(dev, 0);
|
||||
stats->tx_packets++;
|
||||
can_led_event(dev, CAN_LED_EVENT_TX);
|
||||
/* after sending a RTR frame mailbox is in RX mode */
|
||||
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
|
||||
flexcan_write((1 << FLEXCAN_TX_BUF_ID), ®s->iflag1);
|
||||
netif_wake_queue(dev);
|
||||
}
|
||||
@ -801,6 +825,7 @@ static int flexcan_chip_start(struct net_device *dev)
|
||||
struct flexcan_regs __iomem *regs = priv->base;
|
||||
int err;
|
||||
u32 reg_mcr, reg_ctrl;
|
||||
int i;
|
||||
|
||||
/* enable module */
|
||||
err = flexcan_chip_enable(priv);
|
||||
@ -867,8 +892,18 @@ static int flexcan_chip_start(struct net_device *dev)
|
||||
netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
|
||||
flexcan_write(reg_ctrl, ®s->ctrl);
|
||||
|
||||
/* Abort any pending TX, mark Mailbox as INACTIVE */
|
||||
flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
|
||||
/* clear and invalidate all mailboxes first */
|
||||
for (i = FLEXCAN_TX_BUF_ID; i < ARRAY_SIZE(regs->cantxfg); i++) {
|
||||
flexcan_write(FLEXCAN_MB_CODE_RX_INACTIVE,
|
||||
®s->cantxfg[i].can_ctrl);
|
||||
}
|
||||
|
||||
/* Errata ERR005829: mark first TX mailbox as INACTIVE */
|
||||
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
®s->cantxfg[FLEXCAN_TX_BUF_RESERVED].can_ctrl);
|
||||
|
||||
/* mark TX mailbox as INACTIVE */
|
||||
flexcan_write(FLEXCAN_MB_CODE_TX_INACTIVE,
|
||||
®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
|
||||
|
||||
/* acceptance mask/acceptance code (accept everything) */
|
||||
|
@ -70,6 +70,8 @@ struct peak_pci_chan {
|
||||
#define PEAK_PC_104P_DEVICE_ID 0x0006 /* PCAN-PC/104+ cards */
|
||||
#define PEAK_PCI_104E_DEVICE_ID 0x0007 /* PCAN-PCI/104 Express cards */
|
||||
#define PEAK_MPCIE_DEVICE_ID 0x0008 /* The miniPCIe slot cards */
|
||||
#define PEAK_PCIE_OEM_ID 0x0009 /* PCAN-PCI Express OEM */
|
||||
#define PEAK_PCIEC34_DEVICE_ID 0x000A /* PCAN-PCI Express 34 (one channel) */
|
||||
|
||||
#define PEAK_PCI_CHAN_MAX 4
|
||||
|
||||
@ -87,6 +89,7 @@ static const struct pci_device_id peak_pci_tbl[] = {
|
||||
{PEAK_PCI_VENDOR_ID, PEAK_CPCI_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
|
||||
#ifdef CONFIG_CAN_PEAK_PCIEC
|
||||
{PEAK_PCI_VENDOR_ID, PEAK_PCIEC_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
|
||||
{PEAK_PCI_VENDOR_ID, PEAK_PCIEC34_DEVICE_ID, PCI_ANY_ID, PCI_ANY_ID,},
|
||||
#endif
|
||||
{0,}
|
||||
};
|
||||
@ -653,7 +656,8 @@ static int peak_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
* This must be done *before* register_sja1000dev() but
|
||||
* *after* devices linkage
|
||||
*/
|
||||
if (pdev->device == PEAK_PCIEC_DEVICE_ID) {
|
||||
if (pdev->device == PEAK_PCIEC_DEVICE_ID ||
|
||||
pdev->device == PEAK_PCIEC34_DEVICE_ID) {
|
||||
err = peak_pciec_probe(pdev, dev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev,
|
||||
|
Loading…
Reference in New Issue
Block a user